I have taken the below image from the source, i have some slight confusion about how read and writes will operate using the 32RAM shown.

Quad port • One port for synchronous writes and asynchronous reads • Three ports for asynchronous reads

Is ADDRD[4:0] the port responsible for synchronous writes on WA[6:1] and asynchronous reads on the first DPRAM32?

And ADDRC[4:0] - ADDRA[4:0] are the asynchronous reading ports?

Also if a 6input LUT can provide 64memory cells, and DPRAM is 32 memory locations, that means the output must be 2 bits for there to be 32 memory locations. Is this what the DID[0] and DID1 bits are? The 2 bit data bits?

Also, if i write to one DPRAM, does this mean i will write to all DPRAM? Since the Write enable signal WE is connected to all DPRAM32's. How then would someone write a byte of data or 8 bits?

Source: https://www.xilinx.com/support/documentation/user_guides/ug474_7Series_CLB.pdf

enter image description here

  • 1
    \$\begingroup\$ Essentially yes,yes,yes,yes. Easiest way to write 8 bits with this block is to instantiate 4 of them (giving a 32x8 RAM) \$\endgroup\$
    – user16324
    Commented Feb 14, 2021 at 19:10
  • \$\begingroup\$ Also it's somewhat masochistic to use directly the FPGA primitives. 99% of the times Vivado infers memories correctly \$\endgroup\$ Commented Feb 14, 2021 at 19:52
  • \$\begingroup\$ How is this thing even asynchronous for reading if the all the WE are bound to the same WED signals lol? Unless it means asynchronous relative to the clock, does it mean you can read from all DPRAM during a level edge on the clock instead of a rising triggering edge? \$\endgroup\$
    – Yogi Bear
    Commented Feb 15, 2021 at 16:56
  • \$\begingroup\$ @LorenzoMarcantonio oddly enough I've (as an enthusiast only, not a professional) found the opposite: when inferring almost anything it's hard to be sure you actually inferred what you thought you did. If it fails, the synthesizer may try to use up all the LUTs on your chip as distributed RAM, because it can't infer that you're only writing one thing per cycle. Maybe that's only valid since I have an idea of what I want the circuit to look like, rather than the behaviour. \$\endgroup\$ Commented Feb 16, 2021 at 17:57


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