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The ++ operator in Systemverilog is blocking. Is there a nonblocking equivalent to it, or are we bound to use the more verbose x<=x+1 form if we want to keep it nonblocking?

Refer to IEEE Std 1800-2017, section 11.4.2 Increment and decrement operators:

These increment and decrement assignment operators behave as blocking assignments.

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There is no non-blocking equivalent to the ++ operator. It has been suggested for the next revision of the standard.

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