# When the NMOS is connected to VDD and turned off, why does it not block the current completely?

The NMOS is connected to the VDD, but when it is turned off we have VSD=0,435 V. Why is the drop not 1,2 V?

The reason I don't understand this is that when the NMOS is off, we are not able to attract any electrons from the p-substrate in the NMOS, so how does it not completely shut the current off and we have a voltage drop of 1,2 V, instead of 0,435 V?

When we swap the drain and source in the NMOS the drop will be 1,2 V, why does it then work?

Here's another simulation:

Look at the left case. Here when the two NMOS on top are turned off, they have an intermediate voltage drop, but here it doesn't matter where the drain and source are?

• You have reversed S and D, to forward bias the body diode.
– user16324
Commented Feb 15, 2021 at 23:22
• This question is basically a repeat of your last question. If your trying to understand your first question using this simulation, it wont work. The transistors in your first question are not connected like this, they have detached body contacts which are connected in a way that ensure body diodes stay off.
– MAM
Commented Feb 15, 2021 at 23:43
• So while the answers on this post are correct, the body diode stuff do not apply to your original posted circuit. Be careful.
– MAM
Commented Feb 15, 2021 at 23:45
• @AdilMalik Thank you very much for warning me. So in the second simulation do we also not get the body diode problem? The second simulation gives the same answer if we swap the drain and souce at the NMOS. Commented Feb 16, 2021 at 0:44

In your second schematic, left side, you are using NMOS transistors to pull the output high. Since the gate voltage can't get any higher than the drain voltage, the source voltage can only rise until $$\V_{GS} \approx V_{TH}\$$. As many students have learned, you really can't make a non-inverting gate by using NMOS to pull high and PMOS to pull low.
• $V_{GS}$ is the actual voltage from gate to source while $V_{TH}$ is a characteristic of the transistor itself. If you use an NMOS to pull up in a logic gate then the transistor's drain will be connected to the supply voltage. If the logic gate input is coming from other logic gates then that signal will also go no higher than $V_{DD}$. For the transistor to conduct, $V_{GS} \approx V_{TH}$, so the voltage at the source must be less than the gate voltage, meaning less than $V_{DD}$. The output can't rise to $V_{DD}$. Commented Feb 15, 2021 at 23:38
• But in our case we have that $V_G=0V$, $V_D=1,2V$ and $V_S=0,7V$ and we have set $V_{TH}=0,7V$, so we have that $V_S>V_G$, and $V_{GS}=V_G-V_S=-0,7V=(minus)V_{TH}$. I understand that when the gate has 1,2 V, we wont get out 1,2 V at the source, the problem is that when the gate is 0 V, why we wont get 0 V at the souce? Commented Feb 16, 2021 at 0:41