I am studying this application circuit to design the biasing circuit.

I have understood the explanation up to a certain point, but I am stuck at the "Gate bias supply circuits" section. It says that "When the ON/OFF switch is OFF condition, both the gate voltages VGS1 and VGS2 will be set to -4.5V. This is accomplished by pulling the adjust pin of the voltage regulator to ground through a 1kohm resistor (Flags FL2 or FL3 are driven low by the sequencing IC)."

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As the switch position is in "OFF" state, the sequencer will hold the FLAG 2 and 3 to low. When the switch is in "On" state, the sequencer will hold the FLAG 2 and 3 to high impedance open-drain state, then VGS1 and VGS2 are set by the potentiometer adjustments.

The LT3021 is a VLDO regulator and LT1497 is a current feedback amplifier. So using both these chips and based upon the FLAG signal from LM3880 VGS is either -4.35V or can be adjusted through 25K pot.

I am unable to understand the working flow between these chips.

Can somebody explain to me the same or provide some hints for me to proceed further?

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1 Answer 1


When the switch is set to the 'off' position (closed) the LM3880 goes into its 'power down' sequence with each flag output pulling low in turn (FL3/FL2/FL1). FL3 and FL2 pull the adjust pins of the voltage regulators low through 1k resistors, which forces their outputs high because the feedback voltage divider ratio is 10 times higher than normal, causing them to attempt to output a voltage 10 times higher but actually saturating at close to +5 V.

The voltage regulator outputs go to inverting op amps set to a gain of 1, which produces a negative output voltage proportional the positive input voltage. The inputs are at +5 V so the outputs go as close as they can to -5 V (according the datasheet the saturation voltage is ~1 V, so they should go down to ~-4 V).

When the switch is turned to the 'on' position (open) the LM3880 goes though its 'power up' sequence (FL1/FL2/FL3), releasing each flag output in turn and allowing the voltage regulators to operate normally with adjustable output. Again, since the op amps invert the voltage the positive regulator output voltage becomes a negative Gate bias voltage.

  • \$\begingroup\$ I got an idea from your explanation. How does pulling the adjust pin of the regulator to gnd through 1K resistor by flag pins will generate 5V? Can you explain in detail? \$\endgroup\$ Commented Feb 16, 2021 at 10:33
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    \$\begingroup\$ The regulator compares the voltage fed back through the resistor divider to an internal reference voltage. When the feedback voltage is lower it raises the output voltage, and when higher it lowers the output voltage. So the output voltage becomes equal to the reference voltage multiplied by the divider ratio. With a reference of 200mV the output will be 5V when the voltage divider ratio is 5 / 0.2 = 25 (or higher, since with a 5V supply it can't go higher than 5V). When the 1k resistor is switched in the divider ratio is between 44 and 75 depending on the pot position. \$\endgroup\$ Commented Feb 16, 2021 at 21:55

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