In the FIFO design, to compare the rptr and wptr, we are feeding one signal into another clock domain.
The rptr which is coming from the slow clock domain to faster one can be synchronized with sync Flip-flop logic explained in the beginning.
However, the wptr which is coming from fast clock domain to slower clock domain and it cannot be synchronized.
For example, If Write clock faster 10 times than Read Clock, then sync_w2r doesn't sample the wptr which is based on wclk.
AS you can see the above waveform, din[10:0] on the write(fast) clock is sampled by read clk clock(slow). and the din is a write pointer which is encoded by Gray. and dout[10:0] is a signal synchronized signal by read clock(slow)
Actually Gray Encoded pointer signal(dout[10:0]) looks not having a continuously sampled by read clock. you can see the dout[10:0]. It causes a race condition problem. Even Gray encoded signal is synchronized by 2 stage flip-flops. but gray encoded signal does not work to avoid race condition issue at the each of edge sample clock. 1(sampled)-3-2-6(sampled)..go on.. it's actually 2 bits signals were changed from 2'b001 to 2'b110.
how can we explain the Gray encoded signal can be used to avoid a race-condition problem?
How is the problem solved?