enter image description here

In the FIFO design, to compare the rptr and wptr, we are feeding one signal into another clock domain.

The rptr which is coming from the slow clock domain to faster one can be synchronized with sync Flip-flop logic explained in the beginning.

However, the wptr which is coming from fast clock domain to slower clock domain and it cannot be synchronized.

For example, If Write clock faster 10 times than Read Clock, then sync_w2r doesn't sample the wptr which is based on wclk.

enter image description here AS you can see the above waveform, din[10:0] on the write(fast) clock is sampled by read clk clock(slow). and the din is a write pointer which is encoded by Gray. and dout[10:0] is a signal synchronized signal by read clock(slow)

Actually Gray Encoded pointer signal(dout[10:0]) looks not having a continuously sampled by read clock. you can see the dout[10:0]. It causes a race condition problem. Even Gray encoded signal is synchronized by 2 stage flip-flops. but gray encoded signal does not work to avoid race condition issue at the each of edge sample clock. 1(sampled)-3-2-6(sampled)..go on.. it's actually 2 bits signals were changed from 2'b001 to 2'b110.

how can we explain the Gray encoded signal can be used to avoid a race-condition problem?

How is the problem solved?

  • \$\begingroup\$ What do you mean by "doesn't sample"? \$\endgroup\$
    – user253751
    Feb 16 at 15:53
  • \$\begingroup\$ @user253751 sync_w2r sampled by rclk. it's slow for sampling a wptr \$\endgroup\$
    – Carter
    Feb 17 at 1:12
  • 1
    \$\begingroup\$ There is a whole paper on this by Cummings. + There are many resources in online. Closing. \$\endgroup\$
    – Mitu Raj
    Feb 17 at 4:54
  • \$\begingroup\$ There is no 'missing'. Even if write clock is 10 times faster, read clock will sample it at some point in future. Suppose, by the time read clock arrived, write pointer has just counted up to 3 from 0. The read clock will never sample a 'wrong' value because of gray encoding. It will either be the older value of the write pointer, 2 or the current value of the write pointer, 3. \$\endgroup\$
    – Mitu Raj
    Feb 17 at 6:49
  • 1
    \$\begingroup\$ @Carter, Dave Tweed has already answered your question about missing sequence numbers, i.e. a slow clock will always miss some clock events of a faster clock no matter whether it's sampling a Gray counter or a binary counter (and the sync buffer will ensure a valid sample whether delayed or current). As for races, the frequency of wclk needs to be lower than FMAX of the design to ensure timing closure, i.e. to prevent unfinished combinational logic that generates wptr overlapping setup and hold times of the sync buffer flip flops. \$\endgroup\$
    – tim
    Feb 18 at 15:58

Obviously, the slow side of the FIFO is not going to see every state of the fast-side counter when it is counting at full speed. Fortunately, with proper design, such as using Gray code to transfer the values between clock domains, this doesn't matter at all. When the slow sample occurs, it will get some valid value of the fast counter, or at worst, one of two adjacent values if a bit happens to go metastable.

And of course, once the fast side pauses in its counting, the slow side will get the correct final value of the counter after the synchronizer delay.

I wrote this up in a lot more detail here: gray code clock domain crossing FIFO fast to slow

  • \$\begingroup\$ Sir, I've updated my question. \$\endgroup\$
    – Carter
    Feb 17 at 5:12
  • 1
    \$\begingroup\$ You just repeated statements that you made before. Since you added no new information, I have nothing to add to my answer. \$\endgroup\$
    – Dave Tweed
    Feb 17 at 11:58

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