I want to transfer a couple of bits between two clocks, so I build a small handshake logic, but my timing analyzer shows me some violations.

Setup/hold violations and in addition some rule check violations, about un-constrained asynchrous data transfer. I guess this is all related to some missing constrains.

I tried using multi-cycle constrains, but this didn't do much. (The clocks both use the same frequency so I assume this to be wrong anyway?)

The design, despite the violations works, but I still want to get rid of the / understand what's going on. Maybe someone here has experience in this field. When everything is derived from one common clock using a pll I never had such a problem, my first time working with a rather big fpga and multiple external clocks.

In case this helps:

  • Software Quartus PRO
  • FPGA Stratix 10
  • DE10PRO (Board from terrasic)


The clocks should be unrelated and they are not derived from the same source (atleast not inside the fpga)

A bit more information:

  1. (clk_sys) The first clock I get from a clock pin and change it using a pll inside the fpga (pll to make sure it has the same frequency as the following ones)
  2. (clk_tx) This one is provided by a transceiver ip inside my fpga
  3. (clk_rx) This one is provided by a transceiver ip inside my fpga

The transceiver uses an external reverence clock which is in turn generated by an external pll.

What I want to do is transfering the tx data from my user logic to my transceiver and the rx data from the transceiver to my user logic.

The whole design works more or less as a fast network card using fiber optics. (So there are even more clocks inside the design, like pci-e and even some ddr4 for logging purpose, but for the I used an avalon bus, which takes care of clock-crossing. Only for the transceiver I had to use user logic)


Yes my question is how to transfer data safely between 2 clock domains without warnings from my timinanalyer.

As I have a handshake inbetween with multiple stages synchronisation register for the control signal I'm confident my transfered data is stable at the time. But my analyzer doesn't seem to recognize it (?).

  • \$\begingroup\$ You are expecting a lot from very little info. \$\endgroup\$ Commented Feb 16, 2021 at 17:50
  • 1
    \$\begingroup\$ There is the seed of a good question here about how to transfer a signal between clock domains without warnings. \$\endgroup\$ Commented Feb 16, 2021 at 17:53
  • \$\begingroup\$ Are the two clocks related - derived from a common frequency source? Or are they truly asynchronous with respect to one another? \$\endgroup\$
    – SteveSh
    Commented Feb 16, 2021 at 18:46
  • \$\begingroup\$ Thanks for the feedback as it seemed that my question was lacking informations I added more background and hopefully clarified the question. \$\endgroup\$
    – Darki
    Commented Feb 17, 2021 at 10:02

1 Answer 1


If the two clock domains are truly asynchronous to each other, then your constraints need to treat them as a false path (set_false_path) to exclude them from static timing analysis. Your handshake logic needs to be designed with appropriate synchronizers, and be designed to deal with the handshake latency (add skid buffers if necessary.)

Regardless, any time you have a clock boundary cross you need to deal with handshake latency and skew. If you're using AXI (and you should), consider using AXI register slices to isolate the clock regions. This will help your system close timing using robust, proven logic.

tl; dr: use AXI register slices for sync clocks, or AXI FIFOs for async clocks. Don't reinvent the wheel if you don't have to.


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