Does Quartus support UVM in files with .sv extension?

Question

I want to learn UVM later (i am starting with verilog first, systemverilog is next) but i have this doubt in my head, i have seem examples in the web but they use Modelsim, so my doubt is, if i make a testbench in Quartus with extension .sv, using UVM classes, will it run the simulation? Is it even possible to use the UVM classes in quartus?

I ask this because i know that quartus does not support systemverilog completely like unions, or dynamic arrays, etc. (https://www.intel.com/content/www/us/en/programmable/quartushelp/13.0/mergedProjects/hdl/vlog/vlog_list_sys_vlog.htm).

If it is actually possible to implement UVM in quartus, which i think it does because quartus run modelsim as a simulator, can anyone provide me some link/book/etc about it? i mean using uvm with quartus.

Answer 1

Quartus is for FPGA technology. AFAIK, UVM stuff is mainly used for ASIC-based designs. I will be surprised to see UVM being used for FPGA designs. BTW, you look right in your approach to learn Verilog first then SystemVerilog and UVM later. Modelsim is the third-party simulator supported by Intel's Quartus for waveform simulations. That doesn't imply that it will run UVM on Quartus. It does have all those UVM libraries but that's because Modelsim is used in the industry for ASIC designs as well.

I hope this info helps you. You can check edaplayground for your UVM learnings.