I want to learn UVM later (i am starting with verilog first, systemverilog is next) but i have this doubt in my head, i have seem examples in the web but they use Modelsim, so my doubt is, if i make a testbench in Quartus with extension .sv, using UVM classes, will it run the simulation? Is it even possible to use the UVM classes in quartus?
I ask this because i know that quartus does not support systemverilog completely like unions, or dynamic arrays, etc. (https://www.intel.com/content/www/us/en/programmable/quartushelp/13.0/mergedProjects/hdl/vlog/vlog_list_sys_vlog.htm).
If it is actually possible to implement UVM in quartus, which i think it does because quartus run modelsim as a simulator, can anyone provide me some link/book/etc about it? i mean using uvm with quartus.