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In CMOS circuit design, we know dynamic power is proportional to \$V_{dd}^2Cf\$, so the best way to reduce dynamic power is to reduce \$V_{dd}\$.

However, according to the textbook,

Keeping the same clock frequency becomes unsustainable as \$V_{dd}\$ is continuously reduced, because the rise and fall times of signals stop meeting the noise margin of the gate.

Source: Page 47, Chapter 2, Section 2.5, Parallel Computer Organization and Design By Michel Dubois, Murali Annavaram, Per Stenström. Google books link

I don't understand why rise time and fall time increases as voltage decreases.

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    \$\begingroup\$ What are you talking about? Add more context. \$\endgroup\$
    – Mitu Raj
    Feb 17 '21 at 5:29
  • \$\begingroup\$ Thank you for your advice. \$\endgroup\$
    – Lei Gao
    Feb 17 '21 at 5:34
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    \$\begingroup\$ I am voting to close this question because it needs more clarity. Even if the answers happen to satisfy the OP, someone who reads this question in the future will have no idea what is meant. Please add context so that this question is clear to future readers. \$\endgroup\$ Feb 18 '21 at 15:15
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Decreasing the voltage decreases the maximum frequency that can be used such that the operation of the digital system is as desired.

This is because the equivalent resistance, \$R_{eq}\$, of the CMOS transistor increases as \$V_{dd}\$ decreases. As the equivalent resistance increases the propagation delay of the inverter increases, since the propagation delay is proportional to the equivalent resistance.

The average propagation delay is the average of the high to low propagation time and low to high propagation time. The output rise time and fall time depends on the propagation delay of the transistor.

The equation of propagation delay of the inverter is approximately given by

\$t_p = 0.69*R_{eq}*(C_{in} + C_{ext})\$.

\$C_{in}\$ and \$C_{ext}\$ are the effective internal and effective external capacitances of the gate.

As the propagation delay increases the maximum frequency the circuit can use has to decrease, else it would violate the dynamic discipline of digital circuits. Further reading on dynamic discipline: https://computationstructures.org/notes/sequential_logic/notes.html

Modern computers use Dynamic Voltage and frequency scaling, i.e. the frequency is reduced if the supply voltage is reduced.


I also found additional explanation online:

cmos_reduce_vdd

Fig 5.12 b is the voltage transfer characteristic of a CMOS inverter for the supply voltages of 200 mV, 100 mV, and 50 mV (while keeping the transistor thresholds at the same level). Amazingly enough, we still obtain an inverter characteristic, this while the supply voltage is not even large enough to turn the transistors on! The explanation can be found in the sub-threshold operation of the transistors. The sub-threshold currents are sufficient to switch the gate between low and high levels, and provide enough gain to produce acceptable Voltage Transfer Characteristics.

The very low value of the switching currents ensures a very slow operation but this might be acceptable for some applications (such as watches, for example).

At around 100 mV, we start observing a major deterioration of the gate characteristic. \$V_{OL}\$ and \$V_{OH}\$ are no longer at the supply rails and the transition-region gain approaches 1. The latter turns out to be a fundamental show-stopper. To achieving sufficient gain for use in a digital circuit, it is necessary that the supply must be at least a couple times \$ \psi_{T} = k.T/q \$ (=25 mV at room temperature), the thermal voltage introduced . It turns out that below this same voltage, thermal noise becomes an issue as well, potentially resulting in unreliable operation.

\$V_{DD_{min}} > 2…4k.T/q\$

The above equation presents a true lower bound on supply scaling. It suggests that the only way to get CMOS inverters to operate below 100 mV is to reduce the ambient temperature, or in other words to cool the circuit.

Source for the above figures and explanation: http://bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_f01/Notes/chapter5.pdf

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  • \$\begingroup\$ Going from 5.5 V devices which are 50 ohms nominal to 74ALC’ family 3.6 Vmax which are 25 ohms nominal allows faster rise times with more current.. then lower 1.6V devices have lower Cin etc to 1V CPU’s. Yet within each family range RdsOn rises slightly with lower Vdd and thus there is a wide tolerance of Vol/Iol \$\endgroup\$ Feb 22 '21 at 20:17
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    \$\begingroup\$ The effective resistance increases as \$V_{dd}\$ decreases even if \$V_{dd} > V_{TH}\$...this is not exclusively subthreshold behavior. Also, it is not true in general that "Propagation delay is the average of the high to low propagation time and low to high propagation time." You can use that way if you want, but many datasheets specify two values for propagation delay. \$\endgroup\$ Jul 15 '21 at 16:05
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    \$\begingroup\$ It's just an approximation equation for \$ T_{pd} \$ though, actually the relationship is non-linear and hence they keep a look-up table in the cell library for the delay. Btw \$C_{ext}\$ is not 'external capacitance of gate', it is a combination of load capacitance, and other parasitic capacitance at the output of inverter. \$\endgroup\$
    – Mitu Raj
    Jul 15 '21 at 21:35
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    \$\begingroup\$ "This is because the equivalent resistance, Req, of the CMOS transistor increases as Vdd decreases." That's quite interesting considering that both the breakdown voltage and on-state-resistance of a MOSFET are proportional to channel length. One would think that reducing the supply voltage would also allow a proportional reduction in channel length and thus also on-state-resistance. \$\endgroup\$
    – user4574
    Jul 16 '21 at 1:35
  • \$\begingroup\$ As Vt reduces for different logic families so too does RdsOn and the ratio of operational Vdd max/min which indicates the tradeoffs of transition shootthu currents with margin before Vdd .max for Pd and Vdd.min for unity gain. Where 4000 series logic had with biggest range and thus ratio 18V/3V yet lowest speed \$\endgroup\$ Jul 16 '21 at 7:51
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You can consider the fact that the speed of a CMOS circuit is based on the charging and discharging of capacitive loads (since the gate of of downstream transistors is highly capacitive).

Since \$V_{DD}\$ sets the logic values (HIGH = \$V_{DD}\$, LOW = GND), lowering \$V_{DD}\$ decreases a transistor's ability to sink or source current (consider square law: \$(V_{GS}-V_t)^2\$ directly affected by \$V_{DD}\$).

With less current being sourced/sunk the capacitive nodes will charge and discharge at a slower rate, overall decreasing circuit speed and rise and fall times.

Further, consider rise and fall times are related to di/dt. Rise and fall time are by definition dv/dt. This, however is a result of the charging and discharging capacitances. Two standard equations:

\$V = Q/C\$

\$I = dQ/dt\$

yield that

\$dV/dt = I/C\$.

So with less current sinking/sourcing the rate of change of current will also be lower.

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    \$\begingroup\$ Nice and simple explanation but it's actually dV/dt at the output that's relevant for rise and fall time, and is reduced because of smaller charging/discharging current; dV/dt = I/C. \$\endgroup\$
    – Mitu Raj
    Jul 16 '21 at 16:00
  • \$\begingroup\$ Well yes, rise and fall time are by definition dv/dt , but this is a result of the charging and discharging capacitances. V = Q/C, where I =dQ/dt dV/dt = I/C \$\endgroup\$
    – Jake Hertz
    Jul 21 '21 at 20:07
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I am not in chip design, but in electronics and software area, and "the rise and fall times of signals stop meeting the noise margin of the gate.", makes sense to me. See if this is right:

  1. "Noise margin" is the key word there. Noise margin is fixed (almost) amount. At least, it does not narrow as much as supply voltage reduces.

  2. Input capacitance of the circuit, 'Cin', does not decrease as much as supply voltage reduces.

  3. The voltage at input node is Vin = Vout x (1 - e^(-t/tow)), tow = Rin x Cin, which is an inverse exponential curve.

Thus, when Vdd (Vout) is near noise-margin, Vin takes time (rise, fall) to reach the threshold of the noise-margin.

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  • \$\begingroup\$ But doesn't the threshold also scale with the supply voltage in CMOS ? For intermediate input voltages of a CMOS gate, both N and P MOSFETs will be a bit on. Therefore, the logic threshold should be always round about midway between the supplies. \$\endgroup\$
    – tobalt
    Jul 15 '21 at 18:36
  • \$\begingroup\$ Not the turn on/off threshold, but the "threshold of the noise-margin". Thanks tobalt, for responding. \$\endgroup\$
    – jay
    Jul 15 '21 at 19:51
  • \$\begingroup\$ What do you mean by thresholds of noise margin? You mean Vol, Vil, etc? Also, I am not sure how you concluded your last sentence mathematically from the expression in (3). \$\endgroup\$
    – Mitu Raj
    Jul 15 '21 at 21:16
  • \$\begingroup\$ (1) Yes because Vt accuracy between P and N channel determine transition voltage and noise margin is separate from RdsOn (2) Ciss * RdsOn should be fairly constant w.r.t. Vdd. (3) Vil and Vih are usually defined with margins for temp by 1/3 to 2/3 Vdd by design \$\endgroup\$ Jul 16 '21 at 7:59
  • \$\begingroup\$ I am humbled at your observation, Mitu. Let's try this, could you be able to withdraw this?: t = ln(Vin / Vout) x tow. There, Vin has to meet the noise margin. When Vout decreases, t grows. \$\endgroup\$
    – jay
    Jul 16 '21 at 16:22

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