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I'm in the middle of placing components on my first 4-Layer PCB. Layers are Sig-GND-Vcc-Sig. I2C/SPI/UART, up to 20MHz MCU, nothing exceptionally fancy.

I have decided to check with the community whether I'm doing things right. I use small polygon pours with a pair of vias for the ground connection for small groups of decoupling or bulk caps, so I was wondering if I'm doing it right. Because if not, I better restart while I still haven't wasted too much time on doomed layout.

Here is an example of my boost converter, output of which is supposed to go down to the power plane (which doesn't take the entire layer, but bigger rectangular part of it).

The boost converter itself is this: Datasheet (if anyone wants to have a look; I need 1A at most).

booster

Please, roast my layout and tell me why this is bad and how can I improve it (I don't expect it to be good considering I'm losing 4-layer virginity here). Thank you.

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  • \$\begingroup\$ Can you post a matching schematic? It looks like you are using through-hole caps, when the datasheet specifies ceramic X5R or X7R, any reason why? I assume this is on the top layer? \$\endgroup\$ – Ron Beyer Feb 17 at 16:34
  • \$\begingroup\$ I use only 0402 X7R caps; schematic is at work (will attach tomorrow if it's still needed by then). The holes are empty (meaning not through holes) vias to GND plane and PWR plane \$\endgroup\$ – Ilya Feb 17 at 16:44
  • \$\begingroup\$ Where are the pads for the caps? Are they in the flood-fill and you don't have a thermal? \$\endgroup\$ – Ron Beyer Feb 17 at 16:49
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    \$\begingroup\$ You may have issues with soldering and assembly without the thermals, it is more of an assembly issue than an operation one. \$\endgroup\$ – Ron Beyer Feb 17 at 16:59
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    \$\begingroup\$ Also depending on where those via's are related to the pads, you may have assembly issues with solder wicking. If this is being assembled by a board house, they usually charge more for via-in-pad. \$\endgroup\$ – Ron Beyer Feb 17 at 17:09
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One of the main concern's is the common GND point. A swicher should have the GND on the output caps as the preferred point, which it looks like you've done however 1 via per cap minimum. You may also want to put a 0.1uF cap on the input and output. Not many suppliers mention it, but it is important for EMC. I also tend to add a ferrite bead to the output, it will improve the stability of the PSU if driving a high load capacitance.

0402 caps might be an issue. Have you checked their capacitance at the applied voltage? You might be shocked as to the value. I always try for 0805 or bigger.

I would tend to run the fb loop on the top layer and the en pin lower down the stack, think about what lines are critical, and which don't matter. Maybe also try to make the copper fit the pad, when you hang over the sides, you increase the chance of a short.

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  • \$\begingroup\$ Thank you for your input! I always have 0.1uF on input and output (1 of them). My 0402 are 10uF/16V rating (except the 0.1uF caps with 16V rating), I don't know if I should look at anything else about the caps (and I tried to match the IC's input/output capacitance spec). These 0402 got really beefy as of lately. Unless there is a reason to still use larger caps? But larger caps have more ESR, as far as I know. And how do I check capacitance at the applied voltage? \$\endgroup\$ – Ilya Feb 17 at 22:12
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    \$\begingroup\$ you need to look at the supplier web site... some publish, some don't. But for example a samsung 10uF, 10V (largest 0402 10uF) will be around 28% of its value at 5V weblib.samsungsem.com/mlcc/… \$\endgroup\$ – Simon Feb 21 at 2:12
  • \$\begingroup\$ Learn something new every day, thank you. But if I have, suppose, bulk cap on the line near another component, that should also count for total output capacitance, right? Even if the cap is away and there is more esr due to long trace, it's still output capacitance, right? \$\endgroup\$ – Ilya Feb 21 at 12:07
  • \$\begingroup\$ the output caps should be close to the switcher, otherwise you will get noise due to impedances. \$\endgroup\$ – Simon Feb 22 at 19:32

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