# KiCAD: Weird ratsnest

I am in the process of hooking up the ratsnest in pcbNew, in KiCAD.

I finished with the process, except the last connection.

Here it is:

The upper copper layer is set to Vdd. As you can see, the barrel jack connector is in contact with the upper layer, thus providing Vdd across the upper copper layer.

The pin of the IC is where Vdd should connect. As you can see, it makes contact with the upper copper layer. But the ratsnest remains.

I checked around to see if a trace is blocking the upper copper layer, but as you can see, it is connected.

I tried connecting the Vdd directly with the Vdd of the IC, but the line remains. What is causing this?

EDIT: If i select the upper Vdd trace with Control+click (thanks to Pete W advice) i get this:

When i do the same with the trace that connects to Vdd, i get this:

EDIT2: If i remove the trace that connects to Vdd, then two ratsnests show up:

• It seems to do that occasionally. Sometimes superimposing a thin dummy trace to whichever node it thinks is not connected to the copper zone, will make it happy. Another possibility is a segment of a trace in the path was previously assigned to another node in the netlist, and didn't update. You can investigate by control-clicking (highlight path) the traces involved in the view that is shown. If you figure out the root cause, curious to get an update – Pete W Feb 17 at 23:46
• Thanks! How do i control click? – user1584421 Feb 18 at 0:16
• mouse over any trace, hold down the Ctrl button, then click – Pete W Feb 18 at 0:17
• @PeteW Thank you! I edited the question with the pics. – user1584421 Feb 18 at 0:32
• As you can see, the barrel jack connector is in contact with the upper layer ... no, I can't see a barrel jack ... I see solder pads ... they could be used for anything ... the barrel jack is only visible to your mind ... a phrase like as you can see makes an assumption about what people are thinking – jsotola Feb 18 at 1:46

In order for traces to connect to the zone, they need to have an endpoint inside the zone. Here, you have a trace (the vertical Vdd) that begins and ends outside of the zone fill.

This is logged as https://gitlab.com/kicad/code/kicad/-/issues/1800 in the KiCad issue tracker.

Unfortunately, so far the fix for this will impose performance penalties too great to have it always enabled. We are working toward a long-term fix that will be acceptable.

• ah! so just need to add a stub inside – Pete W Feb 18 at 2:48
• Thanks but i do not understand how the vertical Vdd does not go in the zone. That area which it connects to is part of the zone. Anyway, i managed to solve this. What i did was take all the four red traces that cross the zone, and get them in the bottom layer, so that they don't cross the upper zone. – user1584421 Feb 26 at 14:36

Super thanks to @Seth for explaining why this phenomenon happens (TIL!) To summarize for future reference, 2 techniques to avoid the issue:

(1) can check continuity of nets by Ctrl-click on any trace. Alternatively, from the menus, Inspect -> List Nets, and then click on the node in question from the list, and it will highlight the path in the same way.

(2) for the sake of investigation, can get a clearer view of traces superimposed on copper zones by changing the display mode of the copper zones to outline: From the menus, View -> Drawing Mode -> Wireframe Zones . To restore it to normal, View -> Drawing Mode -> Fill Zones. This is common enough that there are icons for this on the left side bar just below the ratsnest icon.