# Oscillator circuit frequency error

I built the following circuit on a breadboard: Assuming rails of $$\V_{DD}=3\text{ V}\$$ and $$\GND=0 \text{ V}\$$, and an inverter switching threshold in the middle, one can calculate the theoretical period of oscillation as $$\T=2 \ln(3) \text{RC}\$$, which for the values I have translate to a frequency of $$\f = 1/T \approx 4.5 \text{ kHz}\$$. (You can see the exact and more general calculation here). As you can see, a switching threshold not perfectly in the middle is a pretty minor error. But when I built the circuit on the breadboard (verifying all my parts are the right values), I instead got around 5.6 KHz.

What I notice from probing the circuit is that $$\V_1\$$ doesn't get pulled up quite as high or as low as it theoretically should, although the error in the negative direction is more pronounced. Since it doesn't go as low as it should, it gets back up to the switching threshold more quickly and so that part of the period is shorter than expected, thus higher measured frequency.

What's the most likely root cause of this? My first thought is the unequal drive strength of the inverters, although I don't know if this is expected to be a major issue for a discrete CMOS inverter (like I'm using).

• what is the drive strength of your inverters? What are the tolerances of R1 and C1? Other than that: congratulations, you've built a measurement device for stray capacitances on breadboard! Feb 18, 2021 at 9:49
• I'd say you have succeeded in building an RC-based oscillator. The resultant 5.6 kHz output is almost certainly within the tolerances possible by your R and C values as well as the stray capacitance of the wires and breadboard connections. If you need a more accurate oscillator you might want to consider using a crystal or ceramic resonator based oscillator. Feb 18, 2021 at 10:23
• another thing is the switch level of you inverter. Are these at least schmitt triggered? the threshold voltage is quite large and such an oscillator actually depends on the threshold for it's frequency. And often capacitors are 20% tolerance, too. All in all it's performing as designed, if you just need 'some clock' it is suitable. You next step could be a crystal or resonator pierce oscillator (not really more complex than that!) Feb 18, 2021 at 12:26
• transient waveform at "V1" point goes above Vdd momentarily, and also goes below GND momentarily. ESD protection diodes built into inverter-gate input might be clamping the tops and bottoms of these transients. Feb 18, 2021 at 14:12
• @MarcusMüller The drive strength of the inverters is around ~4 ish mA. I think my R/C tolerance are 5% and 10% respectively (not positive on the capacitor one, it says "K5K" on it and from another question on here I think the first "K" mean 10%). Feb 18, 2021 at 17:13

My very old CMOS documentation for this oscillator recommends a slightly different circuit, with an added resistor:

simulate this circuit – Schematic created using CircuitLab

The extra resistor R1 prevents any ESD diodes inside NOT1's input from clipping the RC waveform, whose voltage momentarily exceeds Vdd, and also extends below ground. With R1=0, the oscillator still works, but at a slightly higher frequency, because of the clipping caused by the protection network.

Out of curiosity, a simulation was run on the following LTSpice circuit, using a Philips 2005 model for HCMOS buffered NOT gate:

• With R2=100k, oscillation frequency was 4666 Hz. Close to $$\{1}\over{2\ln(3)R_1C_1}\$$
• With R2=0 ohms, oscillation frequency was 6000 Hz.
• Thanks a lot, this is very interesting. Out of curiosity, for my inverters (datasheet here) there is a table with some values of "input/output clamp currents". I wonder, does that mean it's probably referring to currents that can be supported by diodes like these at the inputs? Feb 19, 2021 at 2:52
• I just ran a test where I tried to input a sine wave directly to the input of the inverter (with a series resistor), and when measuring the actual input potential it ended up clipping at the same voltage as before, ~0.8 volts above VDD, so it does look like there's a diode connected there. Feb 19, 2021 at 3:17
• That TI datasheet spec suggests that those ESD diodes are weak, and can't take more than 20mA without damage, even momentarily. Another document says that upper diode starts conducting for input voltage > (Vdd+0.5V) and the lower diode (actually a transistor) starts conducting for input voltage < (GND-0.5V). Feb 19, 2021 at 3:45
• Hm, I see. I was testing at Vdd = 3.3 V and I observed the input maxing out at around 4.1 V consistently. I had a 10 kohm resistor between the input source and the inverter input so it would've been drawing fairly small current. I'm not sure what to make of it if it should have actually been conducting at Vdd + 0.5. Feb 19, 2021 at 4:08