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I tried to make 2 buttons that can fill a shift register with bits. I work it out in Proteus before soldering.

Description:

  • one can press one of two buttons.
  • pressing the left button shifts in LOW (D) (red LED lights up).
  • the right button shifts in HIGH (D) (green LED lights up).
  • both buttons set CLK to HIGH (CLK) (blue LED lights up).

VCC is 5V

switch circuit:

switches

shift-register:

shiftregister

Datasheet SN74LS595

The buttons seem to work, however, (in Proteus) when pressed HIGH at start the first bit is always missing in the shift register (it doesn't go to HIGH) the second bit shifted in (HIGH or LOW) appears . when pressed LOW at start, or a sequention of lows, do not appear.

It only deliver expected results when I start with a HIGH. Is there a way to solve this, has it something to do with the latching?

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  • \$\begingroup\$ Please clean this schematic up, I couldn't understand what you were doing for a while. Ground goes on the bottom! \$\endgroup\$
    – Hearth
    Feb 18, 2021 at 15:10
  • \$\begingroup\$ please link the datasheet for the 74LS595 in your question, so that readers do not have to go looking for it. \$\endgroup\$ Feb 18, 2021 at 15:10
  • \$\begingroup\$ @MathKeepsMeBusy done. see post. \$\endgroup\$ Feb 18, 2021 at 15:51
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    \$\begingroup\$ My first thought is that your pulldown resistor on D isn't strong enough to pull the input low (it's internally pulled high), but that wouldn't make sense if it works fine after the first bit. \$\endgroup\$
    – Hearth
    Feb 18, 2021 at 15:59
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    \$\begingroup\$ I believe your problem is that you are not debouncing your pushbuttons. This is not an issue in your simulation because ideal switches like you have don't "bounce". But real-world switches don't open or close cleanly and the contacts literally bounce. Since you are clocking your shift-register with the output from a bouncing switch, you get an indeterminate number of clocks with indeterminate data each time you press a button. See: allaboutcircuits.com/technical-articles/… \$\endgroup\$
    – jwh20
    Feb 18, 2021 at 16:28

1 Answer 1

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That is expected behaviour when shift and latch clocks are tied together.

Quote from TI 74HC595 datasheet : "If both clocks are connected together, the shift register always is one clock pulse ahead of the storage register."

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