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I am fairly new to FPGA design and I am working on a project where the FPGA is the SPI Slave.

Are there supposed to be constraints on the Master Clock input signal/ MOSI / Chip select?

What is the importance/reason for constraining inputs?

If so, how are these determined? If you have any suggestions for books or videos which give a deeper explanation I would greatly appreciate it. I just want to learn this so I can implement this module correctly.

Thank you

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  • \$\begingroup\$ Yes, of course there are timing constraints, but this is an extremely broad topic. You should look at the datasheets for several different slave devices and you will see what sort of timing constraints must be specified and met. \$\endgroup\$ Feb 18 at 22:25
  • \$\begingroup\$ If no constraints are given does the synthesizer route based on the fastest routing methods? \$\endgroup\$ Feb 18 at 22:33
  • \$\begingroup\$ You want to determine the setup time for MOSI, that is the time that it is stable before the clock edge. As your spi clock increases, this becomes more critical. In the instance that the logic path for MOSI is too long (as in propagation delay) it might be that MOSi coming into the chip has adequate time, but due to internal delays it is too late for the clock at the register it gets clocked into. Therefore you want a constraint. If the tools can’t meet that constraint, they will tell you. Then its up to you to decide to do it differently, relax your specs etc. \$\endgroup\$
    – Kartman
    Feb 18 at 22:50
  • \$\begingroup\$ Thank you for the responses.. I will do some more research and check some datasheets. I was using the vivado deisng suite and the constraints wizard is confusing to me.. I was not sure was the names of the parameters meant. \$\endgroup\$ Feb 18 at 23:06
  • \$\begingroup\$ Remember that "fastest" is not always best when you must synchronize external signals. You really need to worry about relationships between signals so you can avoid setup and hold problems. If your FPGA logic has its own clock then you also need to synchronize between clock domains and avoid metastability. \$\endgroup\$ Feb 18 at 23:26
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As some of the commenters observed, timing analysis can be a very complex topic. In this answer, I will try to hit some of the important and practical points.

  • Q: Why is it important to constrain timing on your design?
  • A: So that internal (hard) timing constraints are met.

OK, so why is it important to meet internal timing? This fundamentally boils down to the behavior of flip-flops (FFs) in your FPGA. The timing of data relative to clock at each flip flop must meet certain requirements or the flip flop next state is indeterminate. Think of the case where clock and data both change at the same instant at the input of the FF. (what is the correct output value in this case)? This is the gist of most timing issues. So, the idea is to have the data stable for some period before (setup) and after (hold) the clock edge used to capture the data. The tricky part here is that an FPGA is quite flexible on how things are connected inside, and all of the interconnect and logic has measurable, but design and placement dependent, delays associated with it.

The good news here is that modern FPGA (and CPLD) tools make it easy to ensure your circuit will work, if you define some timing constraints. The tools perform the heavy lifting of calculating all the path delays and changing internal placement and routing to meet your constraints (if possible).

The simplest, and most important (IMHO) constraint is to define the maximum frequency of each of your clocks. The FPGA tools will make sure that all internal setup and hold times are met between all of the FFs using that clock. It is a good idea to also constrain your inputs and outputs relative the their related clocks.

The following is not really good advice, but rather a practical observation: At low frequencies, it may be possible to not constrain at all. Especially if the protocol (like SPI) has attributes that naturally provide margin. The tools can identify clocks, and can tell you the max frequency possible for a given clock. You can also determine as-built setup, hold, clock to out parameters. In the absence of constraints, the tools will take a balanced approach to area / performance during compilation.

As an example here: if the SPI_SCLK is 1MHz (or below), you probably don't need to worry about timing being an issue. There is about 500ns of setup and 500ns for hold (data to clock) due to the SPI protocol. That is a lot of margin in a modern programmable.

If you fail to meet (FPGA internal) timing, the circuit behavior can be totally unpredictable. You really want to avoid this.

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