# MOSFET on condition - Relationship between drain-gate voltage and drain-source voltage?

I am trying to learn the relationship between drain-gate (VDG) voltage and drain-source (VDS)voltage? From one of the QA readings in StackE, I understand that drain-gate voltage is less than drain-source voltage at MOSFET on condition. I am not sure how is it possible. At this on condition, drop across drain-source voltage would be so small. With that much of small drop, how (VDG) < (VDS) can be true? Image is taken from here

• It is not necessarily true that $V_{DS}$ will be "so small" when the MOSFET is conducting. In general, there is no guaranteed relationship between $V_{GD}$ (do you mean $V_{GS}$?) and $V_{DS}$. Feb 19, 2021 at 0:53
• From my understanding, the drain voltage has no relationship with the gate voltage. The drain simply receives charge carriers in an NMOS device and provides a current path. You apply a VGS across the MOSFET to control the inversion layer within the FET, this in turn controls the current allowed to flow from drain to source. Feb 19, 2021 at 0:53
• @ElliotAlderson, I am taking about VGD itself. I am curious know how the value of VGD will change as MOSFET change its region of operation from linear to saturation. Feb 19, 2021 at 1:36
• It behaves like a resistor. as it goes from linear to saturation VDS resistance decreases. The effect on the gate is do to the capacitance of the package, external circuit and the die itself.
– Gil
Feb 19, 2021 at 1:43
• In the question you reference, they are asking what happens when you control a MOSFET with a gate voltage that is higher than the voltage the MOSFET is switching. For instance using a MOSFET with a 10V gate drive to control a 5V circuit. They are not referring to the voltage across the MOSFET when the mosfet is conducting.
– K H
Feb 19, 2021 at 3:01

## 1 Answer

The voltage on the drain is independent of the voltage on the gate. To control the device, you control the electric field between the gate and the source. When you apply an electric field to the source-gate region of the device, you change the conduction of the source-drain region by rearranging the charge carriers in that region.