I am trying to learn the relationship between drain-gate (VDG) voltage and drain-source (VDS)voltage? From one of the QA readings in StackE, I understand that drain-gate voltage is less than drain-source voltage at MOSFET on condition. I am not sure how is it possible. At this on condition, drop across drain-source voltage would be so small. With that much of small drop, how (VDG) < (VDS) can be true? Image is taken from here
The voltage on the drain is independent of the voltage on the gate. To control the device, you control the electric field between the gate and the source. When you apply an electric field to the source-gate region of the device, you change the conduction of the source-drain region by rearranging the charge carriers in that region.