I have a top level module that contains instances of other modules.
I simply want to connect the output of one module to the input of the other, like so:
module top_level( ... ); module_a A( .out(my_wire) // line 32 ); module_b B( .in(my_wire) ); wire [7:0] my_wire; // line 51 endmodule
However, modelsim compiler is throwing an error that
** Error (suppressible): /../top_level.v(51): (vlog-2388) 'my_wire' already declared in this scope (top_level) at /../top_level(32)
I've tried removing the my_wire declaration (
wire [7:0] my_wire;) and it compiles OK, but throws an error later because it infers my_wire to be a wire of size 1, when really a wire of size 8 is needed.
What's the recommended way to do this?
I've also tried:
module_a A( .out(in) ); module_b B( .in() );
but unfortunately I have other modules in top_level that have a port named
.in which I don't want it connected to
I found this post https://stackoverflow.com/questions/19327819/output-of-a-module-used-as-input-of-another-in-verilog but the solution didn't work for me. I also saw this post https://stackoverflow.com/questions/56286714/verilog-proper-way-of-connecting-ports but found the answer a little confusing (sorry Oldfart, I have found your answers helpful in the past though)