# Assigning a declared wire to connect ports on two different Verilog modules

I have a top level module that contains instances of other modules.

I simply want to connect the output of one module to the input of the other, like so:

module top_level(
...
);

module_a A(
.out(my_wire)  // line 32
);

module_b B(
.in(my_wire)
);

wire [7:0] my_wire; // line 51

endmodule


However, modelsim compiler is throwing an error that

** Error (suppressible): /../top_level.v(51): (vlog-2388) 'my_wire' already declared in this scope (top_level) at /../top_level(32)

I've tried removing the my_wire declaration (wire [7:0] my_wire;) and it compiles OK, but throws an error later because it infers my_wire to be a wire of size 1, when really a wire of size 8 is needed.

What's the recommended way to do this?

I've also tried:

module_a A(
.out(in)
);
module_b B(
.in()
);


but unfortunately I have other modules in top_level that have a port named .in which I don't want it connected to

I found this post https://stackoverflow.com/questions/19327819/output-of-a-module-used-as-input-of-another-in-verilog but the solution didn't work for me. I also saw this post https://stackoverflow.com/questions/56286714/verilog-proper-way-of-connecting-ports but found the answer a little confusing (sorry Oldfart, I have found your answers helpful in the past though)

• What are on lines 32 and 51? Feb 19, 2021 at 6:42
• Post the code in your submodule. Feb 19, 2021 at 6:42
• To avoid inferring wire width as 1 bit, explicitly include the width: module_a A( .out(my_wire[7:0]) ); module_b B( .in(my_wire[7:0]) ); Feb 19, 2021 at 8:58
• @dave_59 line 51 is wire [7:0] my_wire and and line 32 is the input port on B, .in(my_wire) Feb 19, 2021 at 15:19
• @MarkU just tried that. If I try that on both the the output port and input port, or just the input port alone, I get Error: Undefined variable: 'my_wire'. If I try it on just the output port I get Illegal part-select expression for variable "alu_out" Feb 19, 2021 at 15:28