0
\$\begingroup\$

I have an application where I have a sensor which communicates with an FPGA with about 15 differential pairs of data clocking around 300 Mhz. Due to constraints, the board can't be taller than 35mm and the surface mount header which receives all this high speed data has to go horizontal smack dab right in the middle of the back of the board. This leaves no room on the front of the board for the FPGA not to overlap the sensor header on the back. Now technically they are both surface mounts so you could say it isn't a problem, however the FPGA (Artix7 200T) has high frequency bypass caps requirements which are supposed to be put on the opposite side of it right where the header has placed itself. I am wanting to know if anyone has design horse sense from experience as to know if it is less risky to

  • shift the FPGA 2 to 3 cm off to the side to get it off from behind the headers which would lengthen the differential pairs or
  • Make exceptions for the proximity of the high frequency caps on the back of the FPGA?

I will eventually have more experts looking at this but need initial decision just to get keep things going until I can get to that point.

\$\endgroup\$
3
  • \$\begingroup\$ What is the total length of your diff pairs? \$\endgroup\$
    – SteveSh
    Feb 19 at 20:07
  • \$\begingroup\$ They will probably end up being about 3 to 4 cm long on the main board plus however they have them laid out on the daughter board. \$\endgroup\$
    – Joshua
    Feb 22 at 12:01
  • \$\begingroup\$ So long as you maintain the same characteristic impedance Zo through the entire interface (+/- 10%; +/- 20%), another cm or two on the main board isn't going to impact performance. \$\endgroup\$
    – SteveSh
    Feb 22 at 13:16
0
\$\begingroup\$

If it were me, I would slide the FPGA in order to meet the manufacturer's recommendations for decoupling cap replacement. You have control of the routing from the header to the FPGA.

I think that's an easier problem to manage than trying to do a full up PDN (Power Distribution Model) of your FPGA with the decoupling caps placed in a non-optimum location.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.