I currently have a delay line using a series of flip-flops and buffers which precisely measures the time between rising edges of a start and stop signal. I would like to implement a delay locked loop (DLL) on my FPGA to help reduce error accumulation between flip-flops.
Has anyone designed a DLL on an FPGA before and could provide some useful resources or advice? Most of the information I have found online uses FPGA's with existing DLLs or ASIC designs that use custom DLLs.
Here is my delay line architecture: