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I currently have a delay line using a series of flip-flops and buffers which precisely measures the time between rising edges of a start and stop signal. I would like to implement a delay locked loop (DLL) on my FPGA to help reduce error accumulation between flip-flops.

Has anyone designed a DLL on an FPGA before and could provide some useful resources or advice? Most of the information I have found online uses FPGA's with existing DLLs or ASIC designs that use custom DLLs.

Cheers

Here is my delay line architecture:

enter image description here

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    \$\begingroup\$ this is a ripple clocked system. Very hard to control the timing (your Tau) of the clock unless you place and route manually. And to make them equal ... hmm? \$\endgroup\$ – Henning Larsen Feb 22 at 21:18
  • \$\begingroup\$ This is analog design people's job I would say. \$\endgroup\$ – Mitu Raj Feb 23 at 20:41
  • \$\begingroup\$ Have you considered a ring counter with a VCO? or a long inverter feedback loop Osc, for multi phased clocks \$\endgroup\$ – Tony Stewart EE75 Mar 30 at 23:41
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I strongly advise you flip the design round so that all the D-flops are clocked from the same system-wide clock resource, and that you place the delays on your data. FPGAs work very hard to distribute a clock to all parts of the chip with decent fanout and minimal skew, you want to ride that horse in the direction it's going.

The fun part is going to be persuading high level tools to make any sort of delay in your data path, let alone making them of any particular value. Timing synthesis is dedicated to making delays meet maximum constraints, so you have to be quite creative to achieve definite delays. You would have to take control of the PAR process from the high level tools and provide a full hardware level layout for the components to be used as the delays. One simple way I've used in the past to create a definite delay is to force it to route a signal between two pins on opposite sides of the chip (something the PAR couldn't 'optimise' away), but that would could run out of resources quickly if you wanted many stages.

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You can't implement a DLL as purely digital logic, because the feedback that varies the buffer delay is analog. But the good news is that most FPGA families have DLLs available as built-in "hard" modules.

The bad news is that they generally have a limited number of outputs (less than 8), so the length of your FF chain would be similarly limited.

Many FPGAs also have high-speed SERDES (serializer-deserializer) logic built into the I/O modules. These can sample data typically at 10s of GHz, and would probably be a better approach for what you're trying to do.

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  • \$\begingroup\$ The FPGA I am using does not have DLL's built in, could I maybe use a PLL instead? \$\endgroup\$ – PrematureCorn Feb 23 at 22:05
  • \$\begingroup\$ The difference has been discussed before. It depends on exactly what you've got. Can you be more specific? \$\endgroup\$ – Dave Tweed Feb 24 at 0:54

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