How can one transfer data from PC to FPGA and read back result for test purpose where the data must not get corrupted i.e resend if data integrity was lost or use some other error recovery mechanism. The method must be simple to implement so it does not become a whole project on its own.
This scenario can occur where several kB or few MB of data has to be transferred into a digital design to aid in testing. An example is testing of image processing design.
It is true that using the UART is a very simple solution to such a problem. However, UART does not have elaborate error detection and correction mechanism except the parity bit.
One method could to be create a simple mechanism on top of UART where data is transferred in blocks along with CRC bytes. The receiver end can then send an ACK or NAK and the sender will try again if NAK received. Since the data does not need to be transferred in real-time, this could be a satisfactory solution to this problem. Is there something else that I should look into so as not to reinvent the wheel?
My focus is Intel FPGAs for this question but it would be great if this could work with Microsemi FPGAs as well.