What is the methodology behind 555 timer design?

Question

Small circuits in TTL and RTL we could do intuitively, without any methodology. But what about a complex circuit like 555 timer?

If it was designed using logic gates, it could be easily deduced by using boolean algebra, truth table, k-map, etc. These could be the methodology.

Not intuitive.

The 555 timer was designed with a complex transistor network and some passive components.

I know that transistor building blocks are just what was used to make logic gates, but what methodology used to design the 555 timer, or it was completely intuitive (no methodology?)

Answer 1

The 555 was designed in the late 1960s - early 1970s, then the usual design method for analog ICs was in a nutshell:

1. think up and draw the block diagram

2. translate the blocks from the block diagram into discrete transistor based circuits (resistors and capacitors can be used as well). For some situations you might want to use special test-ICs that contain the real transistors as they are made in the actual IC production process (for high speed or low noise design, this can be crucial, not for an NE555 tough).

3. Build the circuits from 2) and measure them, do calculations, tweak it until the performance is good enough.

4. Draw the final design of the circuit as it is going to be on the chip.

5. Draw the layout and have that processed.

6. Measure your new IC and see if it does what it is supposed to do. If not, find out what is wrong, fix the design and try again.

Source: the columns from Bob Pease here and other stories I read some time ago on how gurus like Pease, Widlar, Gilbert etc. etc. worked long ago.

How do we do that today?

In a very similar way but the "building your circuit with discrete transistors" has been replaced by using a simulator and a PDK (Process Design Package) from the chip-foundry (factory where the ICs are made). So we design with "virtual transistors" as making an IC is expensive and takes a lot of time. In a simulator we can "play" until the cows come home ;-).

Answer 2

If you want to know what methodology was used, I suggest you read the book written by the creator of the NE555, Hans Camenzind (RIP).

The link above is for a free download. You can also buy the printed book. I have both his books in hardcover.

Edit: Jim Williams (RIP), Analog Circuit Design is good too, it's a series of chapters by different folks, including him.

The 555 was introduced in 1972, so the design is about 50 years old now, and predates even SPICE simulation by a few years. When I first used SPICE, it was with text rather than a GUI, and the text was umm printed on Hollerith 80-column cards. And some JCL cards preceding the deck.

Analog IC mask artwork (images) were created by literally cutting rubylith plastic film using an X-acto knife.

Answer 3

I became aware of this timer when I was 19 years old (1979), and the chip itself had come to market only 8 years prior to that; in 1971. The designer Hans Camenzind was clearly an inventor by nature. He'd originally been hired by Signetics to develop a phase-locked loop (PLL) IC, and later designed an oscillator for these. There was definitely a need for this type of device at the time it was designed, as no such device existed then. Experimentation, trial and error methodology perhaps, as suggested by Bimpelrekkie. Microsoft Windows hadn't been invented yet, neither had any type of virtual design software. The man clearly knew his theory, components, and circuit design very well. At the pace things change nowadays, this chip is incredible by any standard, because it has endured the test of time. There's an interesting read at https://en.wikipedia.org/wiki/555_timer_IC though no mention is made as to how he proceeded to accomplish this feat. They do mention that he would have been laid off work due to a recession in 1970, but offered to continue working at home with company equipment. Knowing that the standard 555 package includes 25 transistors, 2 diodes and 15 resistors on a silicon chip does not lessen this incredible achievement. He knew his stuff!

Answer 4

Apart from knowledge of the specific implementation, the general idea (philosophy) of this topology is also of interest.

In essence, the idea of ​​this circuit solution is to artificially make a device with hysteresis by assembling it from several basic elements - one digital (RS latch) and two analog (op-amp comparators with thresholds).

"Hysteresis" means "memory"... but implemented by a 1-input element. However, what do we do when our RS latch has two inputs... and they are driven in the same way... in the same direction (by applying an "active 0" or "active 1")?

Obviously, we have to invert one of them. For this purpose, we make one of the comparators (threshold elements) connected before the R and S inputs, inverting and the other non-inverting. Also, we must take into account that the non-inverting comparator must have a higher threshold than the inverting one. Now, we can join their inputs to obtain a 1-input element with hysteresis.

(I have long had observations on this topology... but I must admit that I fabricated what I wrote above a while ago.)