I am trying to design a full subtractor in SystemVerilog.
I searched on Wikipedia and I found this https://en.wikibooks.org/w/index.php?title=Microprocessor_Design/Add_and_Subtract_Blocks
module full_adder(a, b, cin, cout, s);
input a, b, cin;
output cout, s;
wire temp;
temp = a ^ b;
s = temp ^ cin;
cout = (cin & temp) | (a & b);
endmodule
But this code seems quite lengthy, and works for only the 1-bit case. I am thinking of taking the 2's complement of the second operand to do subtraction, but that would work only for the 1-bit case. 2's complement is by applying the bitwise negation (~
) operator and adding 1
to it.
But this won't be reusable since it works only for the 1-bit case. Is there a more reusable approach?