I'm new to power sequencing and wanting input on the best way to solve this problem.

I have two separate +5V rails on my PCB coming from a rectified wall source and USB. Due to back powering issues, I only want +5V on each rail when both power sources are present. My initial attempt (pictured) was to use discrete MOSFETs as shown, but with nonzero threshold voltages, I'm dropping >1.5V across the FETs. The loading requirements are up to 100mA on the rectifier rail and up to 30mA on the USB rail, with a voltage drop <500mV (although ideally less) on either rail.

Does my design have any potential, or should I be approaching this entirely differently?

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  • \$\begingroup\$ "Due to back powering issues..." - exactly what 'back powering issues' are you having? \$\endgroup\$ – Bruce Abbott Feb 25 at 22:06
  • \$\begingroup\$ The USB rail powers an MCU through an LDO and the rectifier rail powers an octal bus transceiver with inputs from MCU GPIOs. If the USB is powered first and the GPIOs going to the transceiver are not HIGH-Z, power leaks back onto the rectifier rail, which is concerning because the LDO isn't rated for a ton of current. There's no back powering in the opposite direction (i.e. the rectifier rail doesn't leak onto the USB rail), but I'm still interested in making the circuit as robust as possible. \$\endgroup\$ – Nathan B. Feb 25 at 22:53
  • \$\begingroup\$ "USB rail powers an MCU through an LDO... power leaks back onto the rectifier rail" - so the voltage leaking back won't exceed the LDO output voltage (3.3V?), right? \$\endgroup\$ – Bruce Abbott Feb 26 at 4:45
  • \$\begingroup\$ Correct, the voltage leaking onto the rectifier won't exceed the 3.3V LDO voltage \$\endgroup\$ – Nathan B. Feb 26 at 15:53
  • \$\begingroup\$ That's good, because it means the back-feed from the 3.3V side to the 5V side won't be enough to prevent the FETs from turning off when the rectified supply turns off (when using hacktastical's solution). \$\endgroup\$ – Bruce Abbott Feb 26 at 18:09

Yes, there's a way, with a few more components.

Let's talk about your design for a moment. Note that for the load switches to work, the Vgs must enough above the threshold voltage to turn them on fully. Your circuit doesn't do that. While the N-FET gate is at 5V, the drain will never go higher than 5V-Vgs. If the drain goes above that, the FET turns off. So the drop you're seeing (1.5V) from drain to source is the Vgs threshold voltage.

Let's simulate it:

enter image description here

Try it here: Falstad N-FET dual power switch

Not so great, is it? The outputs are not at 5V, and the FETs are actually in the linear region. Not only that, but the behavior isn't clean; the voltage from one 'tracks' the other as it turns on (it's behaving as a FET follower.) Not what you want.

Here's a circuit that uses only MOSFETs, resistors and diodes. Note the P-FET high-side switches:

enter image description here

Simulate it here: Falstad P-FET dual power sequence switch

This circuit has some refinement to better-define the turn-on characteristics. Specifically, the voltage dividers to the N-FET gates set a turn-on threshold of about 3V for each input (1.5V FETs). And, having two N-FETs in series reinforces the AND logic requirement: that both voltages have to be high enough to turn on the P-FETs.

For the N-FET type the plain old 2N7001/MMBT2001 could work, it has a Vgs theshhold of 1 to 2 V. For the P-FET, choose any type that has a low enough Vgs for logic. The FDN306P is a good one for this work.

Finally, you can modify the dividers to set an appropriate threshold, but note the variation of Vgs so don't go too crazy with that. If you need more precision, consider using a power monitor IC.

  • \$\begingroup\$ An excellent answer! Thank you very much. I'm going to prototype this with some FETs I already have, and I bet I'll get better results :) \$\endgroup\$ – Nathan B. Feb 25 at 23:16
  • \$\begingroup\$ Is there a name for this type of ANDing of voltage rails, or is this just something you came up with? \$\endgroup\$ – Nathan B. Feb 25 at 23:16
  • \$\begingroup\$ It's something I came up with. I do lots of power sequence stuff using discretes because they're inexpensive and predictable at power-on. \$\endgroup\$ – hacktastical Feb 25 at 23:24

Your design will never switch on fully as the sources will always be below the gate voltages by at least the threshold voltage for the FETs (more if the load current is significant). Consider using two small n-channel FETs driving the gates of two p-channel FETs, this should give better saturation. Don’t forget some resistors to ensure that all the FETs switch off when the supplies are removed.


With regards to the turn on voltage problem, I think you just need a couple more transistors and select pmosfets with a Vth which will give you a low enough R_on for your required voltage drop. The transistors to turn on the mosfets dont need to be bipolar they can also be fets.


simulate this circuit – Schematic created using CircuitLab

With regards to current sharing and feedback I would recommend some schottky diodes to have a low voltage drop.


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