# Properly simulating a NAND gate? (I'm building a computer in my computer)

I am about to embark on a project, enspired by Nand2Tetris (http://www.nand2tetris.org/), to fully simulate a computer, building the entire thing up from NAND gates.

I want to simulate everything from scratch, starting with a primitive implementation of a NAND gate that simulates how a NAND gate would work on the physical level, and then connect them together to build a computer.

The thing is, I don't understand enough about how a NAND gate would work on the physical level in order to write this.

To be clear, this is certainly not what I am looking for:

def nand(a, b)
return !(a && b)
end


I'd like to implement the NAND gate as a class, so it functions more like an actual object. I'd like it to have pins, and I'd like to be able to connect the pins together and apply voltage, etc.

Can someone show me how you might implement a proper simulation of a physical NAND gate, one that could be linked together to ultimately build a computer?

• While I think what you're doing is great, I think this question is a bit too broad for Stack Overflow. How low-level are you talking about here? At the level of individual transistors? Individual atoms? – templatetypedef Jan 11 '13 at 5:44
• Great question. I think transistors would be a good starting point. Atoms, lets save that for a later project :) – MikeC8 Jan 11 '13 at 7:30
• If your project is to "build the whole thing up from NAND gates," like you say in your first paragraph, then you shouldn't worry about how NAND gates are physically realized. If you do that, you're building the whole thing up from transistors, not from gates. – The Photon Jan 15 '13 at 3:01
• You should have a look at Digital. In particular, have a look at the README file -- it contains some good details about how the program is implemented and various pitfalls that were encountered. – ErikR Jul 18 at 5:05

The best way is to implement an event wheel and define a propagation delay for the gate. Without this delay it is impossible to simulate any kind of memory element. You can look up the term "event wheel" in google, it is the basis for HDL simulators. Alternatively you can write the whole thing in verilog which has the advantage of actually realising the hardware later with the right tools and the simulator can be free (look up "Icarus").

If you really want to apply voltages you will have to implement a transistor model or use BSIM3 in some kind of custom simulator, but you will eventually have to reimplement SPICE since the object model you propose will not work well for circuits where "inputs" are actually wires connected to gates that can load the outputs and change the behaviour of the circuit.

Good luck.

• No, this won't work. You can't assign an arbitrary delay for a gate, that wouldn't meet timing requirements and the circuit would not work – Shashank V M Jul 17 at 14:54
• @ShashankVM, no, you absolutely MUST have a delay in the gate if you want to simulate it properly. Real NAND gates have delays -- it takes time for the signals from the input pins to propagate through the transistors inside the gate. The delay shouldn't be arbitrary -- but it should exist. Oh, and the timing requirements are based on the actual delays of the circuit elements, not the other way around. – Bill Nace Jul 17 at 15:00
• Event driven logic simulations don't use propagation delays under the hood, instead they use the concept of delta-cycles. Propagation delays, if written explicitly, are modeled using the same event-driven techniques. – Shashank V M Jul 17 at 15:52
• @BillNace my point is you can't simply add delays to a logic design and expect the circuit to work. Also, logical simulations use delta cycles and not propagation delays. RTL simulation is often called "zero-delay" simulation – Shashank V M Jul 18 at 5:23

Building up a computer from NAND gates would be painful. But if you wish to go down to the level of voltages and currents, you need a transistor-level simulator such as spice. Perhaps once you have the transistor-one working, you can assume that it work and switch to HDL as you showed and apalopoapa suggested.