Should the vias for decoupling capacitors touch the pads of the capacitor or not

Question

The board in question is a four layer board, with a dedicated ground plane as well as a dedicated power plane. Capacitors are MLCC, imperial 0402 (metric 1005). MCU is an STM32.

The question now is how to combine decoupling capacitors and vias. The best way would be to use plugged via-in-pad, but sadly for this project this is out of the question.

So now the question is whether I should a) connect the vias and with the pads of the capacitdor with traces (for superior manufacturability but inferior impedence) or whether I should b) place the vias so close to the pads of the capacitor, that no traces are needed.

Regarding a): When I leave something like 0.2 mm of distance between the annular ring of the via and the pad of the capacitor, there will be solder mask between the annular ring and the pad of the capacitor. This solder mask will prevent solder paste getting sucked away from the pads of the capacitors, down the vias.

See the 2010 article "Five Via-In-Pad Myths" from cadence.com: "That little mask dam will stop solder from flowing into the via and everybody will be happy." The downside: due the relatively long traces, the inductance will be relatively high. The following picture shows a capacitor (imperial 0402/metric 1005), a 0.2 mm wide trace, a 0.6 mm diameter via (hole size: 0.35 mm) and 0.2 mm distance between the annular ring and the pad of the capacitor (the mask dam mentioned above):

Regarding b):

The second option could lead to problems during assembly (solder paste getting sucked into the via) but will have superior inductance, as the annular rings of the vias overlap with the pads of the capacitor. No traces are used. See the 1997 article "Bypass Capacitor Layout" by Dr. Howard Johnson: "series inductance is impacted favorably by ... vias jammed up next to the pads (no traces)". See this picture in which the right edges of the via holes line up with the left edges of the pads of the capacitor:

Answer 1

If you don't want the solder to be sucked into the via, then the via has to be a bit away from the pad, and a solder mask sliver between them, but you could:

• move the vias so they're closer together to reduce via pair inductance, they don't have to be aligned with the pad centers

• widen the trace from the via to the cap pads to reduce trace inductance, I mean the trace can be as wide as the via and the pad, that doesn't cost extra ;

• widen the trace from VDDA pad to cap pad (again, lower inductance, although it's very short)

Here's a FingerPaintCAD example, a bit ugly but you get the idea, just apply a wider trace width...

If it is super important that this pin has a very low inductance to ground you can also use a lower inductance cap (LLL, NFM). But I don't see a GND pin next to it, which means the manufacturer of the chip didn't think there was a need to create a low inductance power/ground pair, so most likely it does not need any fanciness.

Answer 2

Unless you have a very specific problem you are trying to solve, I would not butt my vias up against the pads. The potential for manufacturing problems is just too high.

The tiny _tiny inductance added by those small traces is (likely) dwarfed by the inductance of the capacitor you are mounting there and will be inconsequential in the vast majority of applications.