The 2 PNPs and 10k resistors form a comparator. This particular arrangement is called a 'common-base' comparator, and is appropriate for applications like this where the input voltage is the same as the available supply and a small amount of comparator's bias current is acceptable.
If the PNPs are matched, then when there is no or small load, Q2's emitter will be lower V than Q1's emitter. Since the bases are common, Q2 has a lower VBE than Q1, and so will conduct less current. You can calculate by how much, but for example, 0 mV will mean 10x less current. Thus (ignoring PNP base currents), the voltage top across R2 will be a lot less than that across R1, and the gate V of the MOSFET will be quite low -- the MOSFET will be 'ON'.
At zero load current, Q2 and Q1's emitters will be at the same V (if the FET is ON), and so R1 & R2 would have equal currents. This would mean that the gate of M1 would be equal to the base go the PNPs (i.e. about 0.7 V below supply) -- and the MOSFET would be off. This is a contradiction -- what happens is that the current that Q2 consumes pulls its emitter lower, thus increasing the VDS drop across the FET -- the circuit will stabilize with some small drop (10's of mV) across the FET
In a reverse load situation (out > in), Q2's emitter will be higher than Q1 -- Q2 will turn on, and pull its collector nearly as high as its emitter; this will makes M1's VGS nearly 0 and it will be off -- no current will flow back.