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Suppose i have 2 non-blocking statements as follows:

    reg x,y;

    initial
    
    begin
    
    x=10; 
    
    y=20;
    
    end

and if I execute this: a)

always @(posedge clk)

x<=y;

always @(posedge clk)

y<=x;

So will the values of x and y get swapped or will there be race condition here? (suppose i print the values in the 2 blocks, right after the assignment). Also will the always blocks run independent of each other? and what's the difference if I do this: b)

always @(posedge clk)

begin

x<=y;

y<=x;

end
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  • \$\begingroup\$ Both are same. It will infer two flip flops like a circular shift register shifting values at clockedge.. In simulation, it will have initial values as in the initial block. \$\endgroup\$
    – Mitu Raj
    Commented Feb 27, 2021 at 16:52
  • \$\begingroup\$ What do you think will happen? There are many similar questions on this site, have you looked through them? \$\endgroup\$ Commented Feb 27, 2021 at 18:25

1 Answer 1

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The two pieces of code are identical in simulation and synthesis; their values will be swapped. Assignments to x and y use their current RHS values and the order of assignments does not matter because the LHS updates happen after both statements have completed.

If you were to print the the values right after the assignment like

always @(posedge clk) begin

                      x<=y;
                      $display("x ",x);
                      end

always @(posedge clk) begin
                      y<=x;
                      $display("y ",y);
                      end

Then there is a race as to which $display statement you will see first, but both will print the current values of x and y, not their updated values.

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