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If I have theses statements:
output reg [7:0] cnt;
initial
cnt=8'b00000001;
always @(posedge clk)
begin
cnt<=cnt<<1;
cnt[0]<=cnt[7];
end
Now in this how to determine whether bits will get shifted first and then assigned or assigned first and then shifted? Because it will then change either cnt[0] or cnt[1] value depending on which executes first
This was already answered in Are Verilog if blocks executed sequentially or concurrently? :
"Statements within an always block are evaluated sequentially, doesn't matter if blocking or non blocking assignments are used - nonblocking assignments are simply deferred assignments, a subsequent nonblocking assignment to the same reg in the same always block will override the first" .
So in your code, at time zero you will have cnt = 1 and at all further times you will have cnt = 0.
