If I have theses statements:

output reg [7:0] cnt;
always @(posedge clk)

Now in this how to determine whether bits will get shifted first and then assigned or assigned first and then shifted? Because it will then change either cnt[0] or cnt[1] value depending on which executes first

  • 1
    \$\begingroup\$ Have you tried to simulate this yourself to see what happens? What do you think will happen? \$\endgroup\$ Feb 28, 2021 at 13:50

1 Answer 1


This was already answered in Are Verilog if blocks executed sequentially or concurrently? :

"Statements within an always block are evaluated sequentially, doesn't matter if blocking or non blocking assignments are used - nonblocking assignments are simply deferred assignments, a subsequent nonblocking assignment to the same reg in the same always block will override the first" .

So in your code, at time zero you will have cnt = 1 and at all further times you will have cnt = 0.

  • \$\begingroup\$ But in non-blocking statements the order doesn't matter but in your case answer does depend as you are saying it depends on the order. \$\endgroup\$ Mar 1, 2021 at 2:25

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