# How do I build and simulate a T Flip-Flop without a reset in SystemVerilog?

The problem I'm facing is closely related to this: https://electronics.stackexchange.com/a/540545/238188 . I found I could not simulate a T Flip-Flop without a reset on Multisim Live.

I found that I could not get a T Flip-Flop without a reset to simulate in SystemVerilog either, but I could get a JK Flip-Flop without a reset to simulate. This is because I can set a JK Flip-Flop to a known state using J = 0, K = 1 or K = 1, J = 0.

The design code:

module t_ff(input logic t, clk, output logic q, q_bar);
parameter HOLD = 1'b0,
TOGGLE = 1'b1;

always_ff @(posedge clk)
case (t)
HOLD: q <= q;
TOGGLE: q <= ~q;
default: q <= 1'bz;
endcase

assign q_bar = ~q;
endmodule



I tried using bit in the testbench, but that did not work either (just as I expected). I understand that a reset is important for a Flip-Flop in IC Design, but can't we build a Flip-Flop without a reset? I think the T Flip-Flop can be used without a reset in applications when the input for the flip-flop comes from another digital circuit.

I also came across this question and answer: Is there a right way of implementing a T flip flop in verilog wrt using reset signal?

But that answer does not mention what should be done if we don't use a reset.

My question arises from this conversation I had with user "Elliot Alderson"

@ElliotAlderson if you design a T Flip-Flop where the only inputs are T and the clock, then there is no way to set the output to a known state in simulation that supports 'X'. Further reading: sutherland-hdl.com/papers/… – Shashank V M Jan 3 at 16:32

@ShashankVM I think you can, with an initial block in Verilog for example. Sutherland writes very useful papers...did you read the first sentence of the second paragraph in Section 7? – Elliot Alderson Jan 3 at 17:42 (Why can't I make flip-flops in logic simulators?)

"Elliot Alderson" says we can use an initial block to set the output to a known state. I followed that comment and read the section of that paper by Sutherland. I found it seems possible according to the paper, but how is it done?

How is this problem handled in Gate-level simulations?

• Use an initial statement to put q in a known state at the beginning of the simulation. This will have no effect on synthesis. – Dave Tweed Feb 28 at 11:24
• That would depend on exactly what syntheses tool you're using to get from RTL to a gate-level design. – Dave Tweed Feb 28 at 12:43
• @DaveTweed I tried what you said using both Cadence and Siemens simulators, but it did not work as I got an error and the simulation halted. Can you give me a testbench that works for you? – Shashank V M Feb 28 at 12:54
• The simulator is modeling how the T flip-flop would really work, unfortunately. As @DaveTweed suggested, look for some non-standard feature in your simulation tool, or use a different flip-flop. – Elliot Alderson Feb 28 at 13:11

As for "how is this handled in gate level simulation", I've done vlsi design in industry for 15 years and I've never seen a T flip flop since college. A TFF without reset is nonsensical since you can never know what the value is. You could conceivably make a circuit that asserts T if the output is 1 through some FSM that activates once, to put the TFF in a known state. I would call that "reset".

But if you insist, some simulators have a mode to randomly initialize every flip flop in the design. This can be helpful for gate level sims.

• I think you will find that there are many questions on this site that are only of academic interest. Sometimes barely even that. Often we get obscure homework questions that must be solved in some specific manner. – Elliot Alderson Mar 1 at 2:32
• Thanks for this great answer! I am still a student and have not got a chance to work in the VLSI Design industry yet. So it is new information to me that a T Flip-Flop without reset is useless, although I had suspected it would be useless in my answer here: electronics.stackexchange.com/a/540545/238188 – Shashank V M Mar 1 at 5:37

Using bit instead of logic in the design, output q will be initialized to 0, since bit is of 2-state type. Using this technique one can verify the logical correctness of a design. This works for simulation, but it hides the fact that the output is not initialized to a known state when the circuit is powered up.

module t_ff(input bit t, clk, output bit q, q_bar);
parameter HOLD = 1'b0,
TOGGLE = 1'b1;

always_ff @(posedge clk)
case (t)
HOLD: q <= q;
TOGGLE: q <= ~q;
default: q <= 1'bz;
endcase

assign q_bar = ~q;
endmodule