Decoupling capacitor arrangement

Question

I came across this decoupling capacitor arrangement on the evaluation board for the AD5791. It decouples the IC AD8676 with 10 caps! I suspect its related to the AD8676 driving the reference inputs and thus requiring significant changes in current draw as new values are set on the AD5791 DAC. However, it seems like a bit of overkill to me and I'm just wondering will I see any significant performance difference between this setup and an alternative with just a 0.1 and 10 uF on each power rail to GND? If the answer is that the extra caps will help in this situation, then what is the optimal placement of the capacitors C28,29 in this diagram between the two voltage rails?

Answer 1

Blockquote It decouples the IC AD8676 with 10 caps!

No, it doesn't. It decouples the AD8676 with 5 caps. The other 5 are for other chips.

An Analog Devices top applications dude drove this home in a seminar in the 90's. The applications details (schematics, decoupling scheme, demo board layouts, etc.) in their documentation has been tweaked to death. ((Everything)) is important, every little detail. If you want the part to deliver the performance they document, you can't change anything. Beyond capacitor values, use the same manufacturer and part number. He was serious - a 16 bit part can become a 12-bit part real fast.

Update: There is no standard way to show decoupling caps on a schematic. Analog devices routinely shows them right at the component pins, but there is a difference between documenting a design and teaching a design. Putting them at each device clutters up the area around the device where clarity is needed the most, which can be more important in a production / testing environment.

I do what you show, pile them up in a corner somewhere so the netlister and BOM creator can find them. I think it is a valid assumption that most designers know what is going on; the ones that don't, ask and learn.

Answer 2

You're supposed to use those caps on different power pins. It only looks like they're all in parallel in schematic form. On a PCB the layout matters.

The schematic at the end of the datasheet shows this.

Answer 3

I would definitely put them on there. And pay close attention to their layout details.

Why in the world would you consider compromising a $100+ DAC board that has world-class (~6 decimal digit - 1ppm) performance (LTZ1000 ovenized voltage reference, ultraprecision op-amps) by trying to economize on a few pennies worth of tiny passives?

Answer 4

• follow the layout of the demo card unless you know better.

This board has insanely low INL of 1 bit in a 20bit DAC and 10x 0.1uF caps have far lower ESR and Higher SRF than one 1uF ceramic cap.

I remember a problem in the late 70’s with the best Burr Brown Hybrid ADC had INL issues which I surmised was due its internal Vref getting ground shift from the TTL currents switch many bits at once in a linear sweep with several dead codes and hysteresis in the opposite direction. They fixed the problem on the next shipment.

The same holds challenge holds true with minimizing Vref changes in a 20bit DAC so extremely low ESR is needed to attenuate ripple from high speed switched capacitance of FETs.

So I am not surprised to see this common solution for solid low ESR supply filtering distributed to every IC. Even so you still need a variety of values with carefully selected S parameters matched to the ESL of DC grid traces to avoid anti-resonance with noise spectrum generated.

Answer 5

Sometimes you don't see any difference whether you use decoupling caps or not. The times when you discover a problem because you didn't put the right caps are really painful, trust me :) because the problems you have look extremely crazy and you never know what's the hell is going on.

Having said that, you should understand why there are these capacitors and make an educated decision. 10uF and 0.1uF cover different frequencies (because of internal ESL, ESR). The total capacitance may be a function of current consumption. And most important- in application notes, you will always find excessive recommendations, most of the times you can relax a bit. Of course, it depends on other aspects of your design and what risks are you prepared to take to save two/four/eight capacitors.