I'm working on a PLL based frequency synthesizer for the 20m amateur radio band. For reference, I've asked questions in relation to this project before (see here). It uses the idea of an offset mixer in the loop to allow fine tuning, while keeping the course steps relatively large (5KHz) to achieve a higher loop bandwidth (around 400Hz). I should add up-front, that this is mainly an educational exercise to discover how PLLs work. If I can get the loop to lock, I'll be more than happy. I'm not looking for the lowest jitter loop or anything like that at this stage.

Here is the block diagram of what I have so far: enter image description here

and here it is on the breadboard (if I can get the concept to work, I'd consider a more professional layout with a smaller number of boards):

enter image description here

Since I'm using an Analog Devices PLL IC (ADF4002), I've used the ADISimPLL application to suggest a loop filter design. The advise I've received on this site and elsewhere is to keep the loop filter as simple as possible to start. I've settled on a simple active filter (shown below) and I can get the loop to lock if I simply have the PLL drive the VCO. So, if I leave out the mixer, LPF and amps the loop will lock using the filter suggested by ADISimPLL. However, adding back the offset components obviously changes aspects of the loop and the filter no longer keeps the loop stable. I can play around with the phase margin in ADISimPLL to try to take account of the phase effects of other components in the loop. Here's the design that allows a 70deg phase margin:

enter image description here

I believe I've successfully reverse engineered the loop gain equation used by ADISimPLL and I can reproduce the open and closed gain bode plots for the loop filter suggested (see my previous question).

The loop equation has the following format (for this type of charge-pump PLL): \$\frac{\frac{{I_{{cp}}}}{2 {\pi} } \frac{2 {\pi} {K_o}}{s} {F}(s)}{N}\$ and the loop filter shown above has the following transfer function: \$\frac{{R_2} s\, {C_2}+1}{s\, {C_2} \left( {R_1} s\, {C_1}+1\right) }\$. What I think I need to do, is alter this equation to account for the extra gain components in my loop and this is where I'm struggling.


By my reasoning, I can ignore the lowpass filter, since it should have negligible effect on phase at the loop bandwidth. I'm not quite sure about the effect of the mixer, but I think the amplifiers will be a problem. Here's the amplifier following the LPF (called Offset Amp on the breadboard):

enter image description here

I chose this amp because it has broadband gain (the previous amp I designed was non-inverting and had practically no gain at the loop BW). Here is the frequency response:

enter image description here

You can see that at the loop bandwidth, it has a lagging phase of approx -18deg and a gain of 11dB.

So, finally to my question: is there any easy way to account for the amplifiers (and mixer??) in the loop apart from working out the transfer function and including that in the loop equation?

I'm thinking, can I take the response given in LTspice and factor that into the ADISimPLL margin allowance or is that just not going to work? Thanks for all your assistance and apologies for the (yet another) long-winded post!

P.S. I feel I'm very close on this since despite the VCO signal hopping around on the scope, I can actually tune it coarsely (somehow the hardware frequency counter in the scope is picking up the changes in frequency but the jitter is really bad).


2 Answers 2


A useful trick when using a simple PLL package to design offset loops is to recognise that this block:

enter image description here

can be treated as an equivalent VCO, in your case by varying Vt, Fout varies from 6.1MHz - 5.6MHz. So if you tell ADIsimPLL to design a PLL to cover this frequency range, with your actual Kv, then you should get appropriate filter values.

One important thing - you are mixing from above so as far as the PLL is concerned, your 'equivalent VCO' has a negative Kv. So when you put the mixer in the loop you are inverting the loop gain and you must compensate for this by telling the ADF4002 to invert the PD gain. If you are not doing this then this is the prime reason why adding the mixer destabilises the loop. It is important that you design the loop to work with your 'effective VCO', if the loop is designed to work with a VCO frequency of 23MHz, then the N value in the loop gain is too high.

  • \$\begingroup\$ As usual, your answers are spot on. I actually raised the question of which frequency to use in the design in an earlier question (and an earlier iteration of this project!) (electronics.stackexchange.com/questions/510113/…). Also, I worked out that my loop is inverting, in the sense that I need to raise the VCO frequency to lower the offset frequency. So, I've set the PD Polarity flag to 1 (positive), where before it was negative. \$\endgroup\$
    – Buck8pe
    Commented Mar 2, 2021 at 8:51
  • \$\begingroup\$ It's actually easy enough to spot an incorrect polarity sense because the PFD simply rails attempting to force the VCO in the wrong direction. If I get a chance later today I'll re-design the loop for the offset frequency and see how that goes. Of course, it's no substitute for actually working it out yourself, which is where @Neil_UK's answer comes in. \$\endgroup\$
    – Buck8pe
    Commented Mar 2, 2021 at 8:55
  • \$\begingroup\$ I assume that the Bandwidth = 475Hz comment you have for the loop filter is the loop bandwidth as reported by ADIsimPLL. In this case, all the significant phase shifts should be accounted for in the ADIsimPLL calculations, and none of the additional filter elements should be significant at 400Hz. If ADIsimPLL designed your PLL at 23MHz rather than the 6MHz, then the 16dB'ish error in N in the loop gain calculation is likely causing instability. Design a 6MHz PLL with Kv = 300kHz/V. \$\endgroup\$
    – Tesla23
    Commented Mar 2, 2021 at 9:19
  • \$\begingroup\$ Yes, apologies I should have made that clearer. Well, actually I had that question in mind. Wouldn't the amps in the loop have some influence on the loop gain? Do I need to account for the (voltage) gain that these amps introduce at the loop bandwidth or is it simply a matter of allowing extra phase margin to account for the delay they introduce (as I've done in my OP, since I've changed the PM from 45deg to 70deg)? \$\endgroup\$
    – Buck8pe
    Commented Mar 2, 2021 at 9:45
  • \$\begingroup\$ The extra amplifiers and your 10MHz LPF will add negligible phase shift at 400Hz. Ignore them for loop gain calculations. Everything you have added between your VCO and the ADF4002 chip will add essentially no phase shift at 400Hz, except the mixing operation that will invert the polarity. \$\endgroup\$
    – Tesla23
    Commented Mar 2, 2021 at 10:06

A 'loop filter' does not 'keep the loop stable'. At best it allows the loop to be stable. However, if you get it wrong, it will destablise the loop.

I notice your loop filter appears to claim a bandwidth of 475 Hz. That is far too close to your hoped-for 400 Hz, and will likely cause instability.

Paradoxically, the loop filter does not set the loop bandwidth. That's done by the loop gain.

First, remove all your filters, or at least remove their effect. Remove the capacitors from any high frequency low pass filters. Replace any capacitors in the low frequency integrator by a short if DC conditions allow. Otherwise replace by a very large (infinite) capacitor. This may extend your lock time, but that will be fixed later when we re-introduce the filters

Once your PLL is clean of filters, we can calculate the gain. Break the loop at a convenient point, anywhere will do.

Worked Example

Break the loop at the input to your 4002 board. Let's apply 1 radian deviation. This will be divided by the 'coarse tuning steps' divider, whatever N that is. Phase gain is 1/N radians/rad.

Now there's a current-output PSD. Take care with the gain of this one, the output current might be specified per radian, or per cycle, or per other phase step. Use an appropriate factor to get k into Amps/radian. Current gain is now k/N amps/rad.

Now into the loop filter. C1 shunts the PSD current. This lowpass filter is above the loop bandwidth, so we open circuit C1, and completely ignore it, for the moment.

The rest of the loop filter is both trickier and simpler than it looks. The opamp end of R1 is held at ground by the action of the opamp virtual ground input. The voltage gain so far is therefore k.R1/N V/rad.

Now deal with C2. This is a lift in gain below the loop bandwidth, so we replace it with a short circuit, or an infinite value capacitor, either way it doesn't affect the gain.

The gain of the opamp stage is now R2/R1, so the voltage gain to the output is (R2/R1).(k.R1/N) = k.R2/N V/rad.

However, we could have got there quicker noting that all the DC current that flows through R1 also flows through R2, so the transresistance gain is R2 anyway. The voltage gain is now R2.k/N V/rad. (1)

This voltage drives the VFO. The VFO has a sensitivity of p Hz/V, so the frequency gain is p.R2.k/N Hz/rad.

The mixer stage might be inverting, however it's not going to change the magnitude of the gain.

Finally, we need to convert the frequency from the mixer to phase at the 4002 input, in the implicit integrator that is the basis of every PLL. This is easy to get wrong, I did first time round.

A frequency deviation of 1 Hz, at a modulation rate of 1 Hz, gives rise to a phase deviation of 1 radian. The gain of the integrator is therefore 1 rad/Hz at 1 Hz, or 1 mrad/Hz at 1 kHz. (2)

Perhaps the easiest way to handle this is to compute the gain round the loop at 1 Hz, and then the loop gain will numerically equal the final loop bandwidth.

So to complete the calculation, at 1 Hz, the integrator gain is 1 rad/Hz, so the entire gain round the loop is p.R2.k/N. This will drop to unity at a frequency of p.R2.k/N Hz, which is the criterion for the loop bandwidth.

Now Handle the Loop Filters

This loop will lock, and will be super-stable. It will have limited rejection of reference high frequency noise, so now we bring the high pass filter C1.R1 down in frequency to improve it. If we need even more rejection than a single RC gives us, then we can use a higher order lowpass filter. Fractional-N synthesisers often use a much higher order passive filter after the PSD to deal with the rising spectrum of hash that's produced by the process.

It will have poor tracking of the reference, so now we bring the broken integrator C2.R2 up in frequency.

The two filters affect the loop gain in opposite directions, so the effect on loop gain and so loop bandwidth is small.

As a crude but useful rule of thumb, a single pole filter will have 45° phase shift at its corner frequency, 30° at twice that, 15° at four times that and so on. You therefore want your high frequency filter to have a corner of around 4*400 = 1600 Hz. You want your low frequency broken integrator to have a break frequency of around 400/4 = 100 Hz.

If you did have a higher order lowpass filter, then you would still need to budget for a small phase shift down at 400 Hz. You could move your low frequency filter down to allow for more phase shift from your high frequency filter. It's the total phase shift budget at the loop bandwidth that matters.

One on the benefits of having both C1 and C2 filters is that the total phase shift over the range 200 Hz to 800 Hz doesn't change by much. This is important if the VFO you are using has a non-linear Hz/V tuning curve, or you adjust the coarse steps divider. As these appear in the loop bandwidth expression, the loop bandwidth will change as these change. Having little change in excess phase shift over a range of loop bandwidths means that stability and settling time will remain largely unaffected by the changes in loop bandwidth.

(1) Does that mean that R1 doesn't do anything? It doesn't do anything at the loop bandwidth, but it does set the time constant of the high frequency filter with C1. It's odd interactions like this that make hope'n'poke adjustment of loop filter components so frustrating when trying to adjust a PLL into stability. Generally, you have to sit down and work it through as in the example above to be able to set the unity gain frequency, the high filter break, and the low filter break independently and correctly.

(2) A simple way to remember this from sort of first principles is to note that if there's a frequency deviation of 1 Hz that's held for 1 second, then there will be a phase change of 1 cycle, or 2pi radians. Taking a peak 1 Hz frequency deviation, and modulating at 1 Hz will clearly give much less phase deviation. It feels to me that 1/6th cycle, one radian, is about the right amount of 'much less', which is confirmed if we do the sums properly.

  • \$\begingroup\$ That's a fine answer Neil and I apologize I realize I mixed the loop filter bandwidth with the PLL loop bandwidth. Actually, the loop filter given has a zero at 88.4Hz and a pole at 2.84KHz. Am I right in thinking they equate to your low and high filters? But, what I really want to know is can this technique be applied to the actual circuit or is this a simulator exercise? If I break the loop at the point where the final (intermediate) amp enters the PLL board how exactly would I measure the open loop gain? \$\endgroup\$
    – Buck8pe
    Commented Mar 1, 2021 at 19:08
  • \$\begingroup\$ In this case, there's also the post offset mixer LPF. Do I open circuit the capacitors in this filter also? I suppose the key phrase is "Change a gain term until it's unity gain at your desired loop bandwidth." So, I assume that means changing the loop filter resistors (R1/R2), is that correct? \$\endgroup\$
    – Buck8pe
    Commented Mar 1, 2021 at 19:21
  • \$\begingroup\$ Apologies for all the questions Neil, but just one more: how do I setup my (opened) loop to compute the 0dB gain point? Do I feed one end of the opened loop with variable frequency that includes my desired loop bandwidth frequency? \$\endgroup\$
    – Buck8pe
    Commented Mar 1, 2021 at 19:45
  • \$\begingroup\$ @Buck8pe Theoretical, simulator and actual, though the latter two may require a big C2 rather than a short if your DC conditions need a cap. R2+C2 is 88 Hz, which equates to my 100 Hz. C1//R1//the_PSD_current_source is the high freq LPF. Compute the open loop gain. One radian PHASE into the PLL board is OK. Divide by UNKNOWN CoarseTuningSteps, PSD to current, current to volts (R1) with R2/R1 gain in the loop filter, volts to freq in the VFO, freq to phase (here is convenient to do this), no change of phase through the mixer, and we're back to the start. At what freq do we get 1 radian here? \$\endgroup\$
    – Neil_UK
    Commented Mar 1, 2021 at 20:18
  • \$\begingroup\$ @Buck8pe The phase shift of a 10 MHz LPF at 400 Hz is sqrt(f*all), so can be ignored. \$\endgroup\$
    – Neil_UK
    Commented Mar 1, 2021 at 20:20

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