I have a 3.3V PWM signal form microcontroller and i want to increase its voltage and current driving capability (at least 10mA source-sink current).

I have designed circuit like on the pic, but a am not quite satisfied how it's works.

To convert voltage level from 3.3V to 10V i have used a simple CS stage. Basing on simulation results i decided to use mos-based push-pull as a output stage (it had much better voltage levels than a bipolar push-pull).

But this design has some flaws:

  1. During PWM state change i am getting a short between 10V and GND. For a short period of time both transistors are half open. It is a result of poor slew rate of a CS stage. I could improve it a bit by reducing a R3 resistance value but it would increase power consumption.

  2. I am not sure if uP can drive a MOS gate. I could add resistor in series with gate, but it would increase a transition time even further and hence a power rail shorts time.

So, im looking for more handy solution or tips how could i improve my design. Maybe IC drivers exists for such a job?

enter image description here

  • 1
    \$\begingroup\$ see electronics.stackexchange.com/q/3348/187920. Then google for "half bridge driver". TI alone has over 60 parts for this, specifically designed to avoid simultaneous FET opening. \$\endgroup\$
    – Maple
    Commented Mar 1, 2021 at 22:11
  • 2
    \$\begingroup\$ M2 turn over, drain to load, source to plus power supply. In your shematic interna diode is always conduct. \$\endgroup\$
    – user263983
    Commented Mar 1, 2021 at 22:34

1 Answer 1


Try this way, maybe it won't short.


simulate this circuit – Schematic created using CircuitLab

The upper PMOS is capsized, so the built-in intrinsic diode is in conduction mode. You should swap Drain and Source to have a correct orientation.

  • 2
    \$\begingroup\$ you might explain why connecting the PMOS right way round makes such a difference... \$\endgroup\$
    – user16324
    Commented Mar 2, 2021 at 14:44
  • \$\begingroup\$ @BrianDrummond Okey-dokey, I have edited the answer with little more detail. \$\endgroup\$ Commented Mar 2, 2021 at 14:54

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