# How to design the value of capacitor for Capacitive DAC based on noise and mismatch analysis?

In order to design the correct value for the capacitor in a capacitive DAC, we need to look at two possible causes of errors. Noise and Mismatch Analysis. sqrt(kT/C) should be less than 1/2 LSB. But, the value of C seems to be very high based on this equation. (For a 14bit DAC its about 1nF) Also how do we bring in mismatch analysis for the DAC to conclude about the capacitor value?

• What voltage is the 14 bit operating at for full scale? Or rather what is the value of Vfull/2^14 for comparison. The values I calculate are fine. Jan 15 '13 at 10:40
• Also explain how you are planning to implement this. Mismatch at the board level and mismatch on the chip level are driven by by different analysis. Jan 15 '13 at 10:50
• Its a capacitive DAC with all caps equal. Using a sample and hold circuit using an op-amp, the output voltage is generated. The cap DAC is used for 5 bits of MSB and the rest of the bits are resolved by RDAC. Since there are 32 caps, does the kT/C noise refer to all the caps or only one cap? Vfull here is 1.2V. Jan 16 '13 at 2:22

The minimal error you need to be comparing against is the performance of an ideal DAC.

If step size is LSB = $1.2/2^{14}$ = 73.2 $uV$

then the error residue will be

LSB$/\sqrt{12}$ = 21.1 $uV$

If you want the noise contribution (RSS addition) to not be noticeable then the kTC noise should be 1/10 of that = 2.1 $uV$

Which means that the capacitor size is 907 pF or ~ 1 nF using the kTC calculation.

The kTC noise is developed across what ever is being reset. To answer your question you will have to give a schematic. If the Capacitor is being reset from a voltage source or other capacitors, and if there are other Capacitors attached and how that charge equilibrates and the impact of charge conservation.

• Thanks! The value of capacitor does make sense. Just to let you know, a value of 400fF was deemed good enough by the designer while doing this DAC. Its a capacitive DAC with 32 equal caps each able to connect either to 1.8V or 1.2V during sampling phase. During holding phase, the same plate is now connected to output giving us the binary weighted output. 14th bit is just there to change the polarity of Vfull from 1.8V to 0.6V. Hence, we get a 14 bit DAC from 1.8V to 0.6V with 1 sign bit, 5 bits MSB resolved by Cap DAC and 8 bits by RDAC which is connected to one of the caps. Jan 16 '13 at 11:19