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in many application notes for processors in a BGA package I see a declaration that you could fully fanout the bga using only 4-6 layers and almost no HDI technology like microvias, burried vias even for high speed signals like DDR,USB etc. For example in the application note for the STM32MP1 on page 46 ff. you can see their 4 layer stack up with µV only from L1 to L2. On page 50 you see they achieve this fanout by using the top and bottom layer for signals and L2 and L3 for VCC/GND reference plane.

Fanout

But is it such a good idea to route highspeed signals like DDR, USB on the outer layers? I always thought they are best routed in the inside sandwiched between reference planes. This way they are well shielded an protected from environmental influences or is this just overengineering and too expensive? Is this 4 layer layout just a marketing stunt or is this kind of fanout really used in industry, because its cheaper and reliable enough?

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It is normal for a 4 layer board to have two inner layers as GND and VCC, which provides least impedance supply planes, and so the top and bottom layers have only one plane for reference and no other plane with any signals nearby.

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Signals travel marginally faster on outer layers (because the effective dielectric constant is lower) and therefore have slightly lower signal loss (due to dielectric absorption) for a given distance.

This is actually something to keep in mind when routing groups of signals; if some travel on inner layers, it can throw the effective length match rules should there be any.

A single reference plane can actually be an advantage (don't have to worry about how symmetric or otherwise the effective spacings to two layers happen to be).

Typical propagation velocities for most flavours of FR-4:

Outer layers - 160 ps / inch

Inner layers - 175 ps / inch.

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