When I am trying to do simulation of the following program on Modelsim Altera 10.0d then gives Error : Code Error 9: ** Fatal: (vsim-4) * Memory allocation failure.
Attempting to allocate 131072 bytes
Please check your system for available memory and swap space.
The following is my code :-
module sipo (gsclk, sclk, rst, sipo_in, sipo_out, sipo_out_i, dcsel, blank, gs_enable);
input gsclk, sclk, rst;
input sipo_in;
input dcsel, blank;
output reg [47:0] sipo_out;
output reg [47:0] sipo_out_i;
output gs_enable;
integer i;
assign gs_enable = (~dcsel & sclk==1'b1) ? 1'b1 : 1'b0;
always @(posedge gsclk, posedge rst)
i=0;
begin
if (rst)
sipo_out_i <= 47'b0;
else
if (gs_enable)
for (i=1; i<= 48; i=i+1)
@(posedge sclk)
while (i < 48)
begin
sipo_out_i <= {sipo_out_i[46:0], sipo_in};
i = i+1;
end
sipo_out <= sipo_out_i;
end
Please help me if it requires any change in verilog code?