When I am trying to do simulation of the following program on Modelsim Altera 10.0d then gives Error : Code Error 9: ** Fatal: (vsim-4) * Memory allocation failure.

Attempting to allocate 131072 bytes

Please check your system for available memory and swap space.

The following is my code :-

module sipo (gsclk, sclk, rst, sipo_in, sipo_out, sipo_out_i, dcsel, blank, gs_enable);
   input gsclk, sclk, rst;
   input sipo_in;
   input dcsel, blank;
   output reg [47:0] sipo_out;
   output reg [47:0] sipo_out_i;
   output     gs_enable;
   integer i;

   assign  gs_enable = (~dcsel & sclk==1'b1) ? 1'b1 : 1'b0;

   always @(posedge gsclk, posedge rst)
     if (rst)
       sipo_out_i  <= 47'b0;
       if (gs_enable)
         for (i=1; i<= 48; i=i+1)
           @(posedge sclk)
             while (i < 48)
               sipo_out_i  <= {sipo_out_i[46:0], sipo_in}; 
               i = i+1;
           sipo_out <= sipo_out_i;

Please help me if it requires any change in verilog code?


1 Answer 1


Your simulator should be giving syntax errors before the memory allocation error.

The always block has many errors. First it delete the line i=0;, it is assigned in the for-loop. This allows the begin block called on the always blocks triggered events. Don't use both for-loop and while-loop. Currently both dependent on i and if the code could run you would see i go 1 to 48 with no step in between, and sip_out_i would equal {48{sipo_in}}. Assuming not what you are intending and inefficient if it is.

Having a @(...) nested statement inside another block is legal verilog, but is a bad coding style. Synthesis tools and linting tools will give errors. Nested @(...) and wait statements are more intended for the test-bench framework, and even that is mostly discouraged.

You should use two always blocks. One running on gsclk and the other on sclk. sclk should fill sipo_out_i. gsclk transfer sipo_out_i to sipo_out. Handshake signals will be needed to synchronize the two blocks.


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