Error is concurrent assignment to a non-net "c" is not permitted.

module ha (sum,carry,x,y);
  input x,y;
  output sum,carry;
  assign sum = x^y;
  assign carry = x&y;

module vedic_2bit(a,b,clk,rst,c);
  input clk,rst;
  input [1:0] a,b;
  output reg [3:0] c;
  reg [3:0] t;
  always@(posedge clk)
        c <= 0;
        c[0] <= a[0]&b[0];
        t[0] <= a[1]&b[0];
        t[1] <= a[0]&b[1];
        t[2] <= a[1]&b[1];
  ha H1 (c[1],t[3],t[0],t[1]);
  ha H2 (c[2],c[3],t[2],t[3]);
  • 1
    \$\begingroup\$ Use in-built code editor to format your code in the question \$\endgroup\$
    – Mitu Raj
    Mar 3, 2021 at 3:32
  • \$\begingroup\$ What are you trying to achieve? You are driving register c from both modules. \$\endgroup\$
    – Mitu Raj
    Mar 3, 2021 at 4:36
  • 1
    \$\begingroup\$ You defined c as a variable type (reg). Module puts need to be connected to a net-type (ex wire). However a wire cannot be assigned in a procedural code (ex always block). So you need to think how to assign some bits to from a module and other from procedural. \$\endgroup\$
    – Greg
    Mar 3, 2021 at 4:37
  • \$\begingroup\$ And avoid this amateurish port-mapping format ha H1 (, , ,) which can introduce 'invisible' bugs. Use associative port mapping ha H1 ( .(something) => something , ......) \$\endgroup\$
    – Mitu Raj
    Mar 3, 2021 at 4:44

1 Answer 1


Looks to me like the problem is that c[1], c[2] and c[3] are assigned by the rst part of your clocked process, and you're also trying to give them combinatorial assignments by wiring them up to the module below. c[0] is actually fine.


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