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I couldn't find anything in the Verilog-2001 standard about this. For example, the following code works (Xilinx ISE):

reg r1;
always @(posedge clk or posedge rst) begin    
    if (rst) begin
        r1 <= 0;
    end else begin
        r1 <= r1;
        if (cond1) begin
            r1 <= 1'b1;
        end 
    end
end

In this case, r1 is updated to 1'b1 when cond1 is nonzero (@ posedge of clk), otherwise it retains its value (as intended). Similarly:

1 reg [1023:0] a_reg;
2 always @(posedge trigger or posedge rst) begin    
3     if (rst) begin
4         a_reg <= 0;
5     end else begin
6         a_reg <= a_reg; // required?
7         a_reg[i*2 +: 2] <= input; 
8     end
9 end

Is line 6 required? What is considered acceptable practice for FPGA and ASIC design? I would imagine line 6 is not required (as per the definition of a register, it should hold its value between assignments). Or does it depend on the compiler / synthesis tool (DC Compiler, Xilinx ISE/Vivado, Altera Quartus, etc)? Is there something in the standard that sheds light on this?

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1 Answer 1

5
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r1 <= r1 is not required in any synthesiser, as it is in the definition of RTL. Since the logic is written under @posedge clk, it is implicit that the previous value of a the register r1 should be held in that clock cycle if r1 is not driven any value at that clock edge ie., in this case, if the condition cond1 is violated.

This is true for the second example as well. The a_reg vector is formed by 1024 1-bit registers. Therefore the earlier conclusion we made on 1-bit register r1, is applicable to each register in a_reg vector as well.

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2
  • \$\begingroup\$ Would you happen to have a source or material which covers this? Or is this just implied in the Verilog standard? \$\endgroup\$
    – Ralph
    Commented Mar 4, 2021 at 19:48
  • 1
    \$\begingroup\$ This is implied for a sequential logic written in any RTL. \$\endgroup\$
    – Mitu Raj
    Commented Mar 4, 2021 at 19:52

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