I couldn't find anything in the Verilog-2001 standard about this. For example, the following code works (Xilinx ISE):
reg r1; always @(posedge clk or posedge rst) begin if (rst) begin r1 <= 0; end else begin r1 <= r1; if (cond1) begin r1 <= 1'b1; end end end
In this case, r1 is updated to 1'b1 when
cond1 is nonzero (@ posedge of clk), otherwise it retains its value (as intended). Similarly:
1 reg [1023:0] a_reg; 2 always @(posedge trigger or posedge rst) begin 3 if (rst) begin 4 a_reg <= 0; 5 end else begin 6 a_reg <= a_reg; // required? 7 a_reg[i*2 +: 2] <= input; 8 end 9 end
Is line 6 required? What is considered acceptable practice for FPGA and ASIC design? I would imagine line 6 is not required (as per the definition of a register, it should hold its value between assignments). Or does it depend on the compiler / synthesis tool (DC Compiler, Xilinx ISE/Vivado, Altera Quartus, etc)? Is there something in the standard that sheds light on this?