I have a question about the process that I wrote to divider a 1MHz clock down to a 10kHz clock.
I don't know why my code always splits up like it does below, if someone can edit it to look better and let me know what I am doing wrong.
Now my question is how are the if and elsif statements inside the process performed? On the rising edge of the clock, the Count signal will be incremented by 1. But will the elsif statement ever be executed as the if statement will have to be true?
Include libraries / packages Entity Clock_Divider is Port (Clock_in : in std_logic; Clock_out : out std_logic ); end Clock_Divider; Architecture Behavioral of Clock_Divider is signal Count : integer := 1; signal Temp : std_logic := '0'; begin Process (Clock_in) begin if (rising_edge(Clock_in)) then Count <= Count + 1; elsif (Count = 100000) then Temp <= not Temp; end if; Clock_out <= Temp; end Process; end Behavioral;