0
\$\begingroup\$

I'm trying to create a circuit that will make the output go high some amount of time after a 5V control signal goes high. That delay time may vary by application, so I'll use a potentiometer in place of the 249k resistor. I'm thinking of using a 555 timer in monostable with a 5V power supply. Below is the circuit I came up with, and I think it will work, it just seems like I might be coming up with something that's overly complicated because I'm a n00b. Is this a good approach, or is there a simpler/more effective way to do it?

EDIT: One other requirement that I neglected to mention. I want the delayed output to go high after some time, but I also want it to go back low immediately after the input goes low. I feel like that might cause a problem with using an RC filter.

enter image description here

\$\endgroup\$
3
  • 2
    \$\begingroup\$ A comparator with RC in the input? \$\endgroup\$ – Eugene Sh. Mar 4 at 19:31
  • 1
    \$\begingroup\$ There are power monitor and reset circuits that may be able to do this. Otherwise RC into a Schmitt trigger buffer. If the Schmitt trigger is not precise enough you can use an analog comparator. \$\endgroup\$ – mkeith Mar 4 at 20:30
  • \$\begingroup\$ I don't think the circuit you posted will do what you want. How do you think the R-C discharge-Threshold node behaves? Also, please add reference designators to all components. \$\endgroup\$ – AnalogKid Mar 5 at 1:00
0
\$\begingroup\$

A problem with the 555 in your application is that the 555 was designed from the ground up to use a capacitor that is charged from ground up. To do what you want requires at least one external inverting, device, like a transistor or logic gate.

An alternative is a delay generator made with the gates of a CD4093 quad NAND Schmitt trigger gate. Using a Schmitt trigger gate eliminates a noise burst that is almost guaranteed by the very slow risetime of the large R-C network.

When the input goes from low to high, the output goes from low to high after an R-C delay. When the input returns low, the output goes low immediately. If the time between activations is longer than the delay time, then the circuit will recover nicely. If the time between activations is less than the delay time, adding diode D1 resets the timing capacitor much more quickly.

First pass at a schematic:

enter image description here

UPDATE: This also can be done with three sections of an AND gate, plus one resistor to create a bit of hysteresis.

\$\endgroup\$
0
\$\begingroup\$

If your delayed signal feed some TTL logic which has 2.5V treshold, then just use circuit like this. The delay is time until cap gets charged to 2.5V.

enter image description here

The disadvantage is that the delayed signal stays ON for a same while after controll signal gets OFF. Also consider if controll signal is strong enough to charge cap thru 10k without affecting it.

\$\endgroup\$
1
  • \$\begingroup\$ A diode can be used in parallel with R1 to force them to turn off at the same time. If you connect delayed Sig to a Schmitt trigger logic input or analog comparator input you will have a pretty decent delay circuit. \$\endgroup\$ – mkeith Mar 4 at 20:32
0
\$\begingroup\$

Here is another version of a signal delay circuit. This one uses only three gates. Another possible advantage is that it powers up in the waiting-for-activation state. That is, the initial output state is low if the input is high at power-up. With the other circuit, if the input is high at power-up the output goes high immediately.

U2C is unused. R2 is added to create hysteresis at the U2B inputs. This prevents a U2B output noise burst as its input voltage increases slowly through its transition region.

When the input goes high, U2A pin3 goes high. But C1 is still discharged so U2B pin 4 is still low. R1 and R2 form a voltage divider between the high and low outputs, and the centerpoint voltage is what charges C1. With the values shown, the max voltage across C1 is 0.8 x Vcc, which is greater than the gate's input transition voltage of approx. 0.5 x Vcc. When the capacitor voltage crosses above approx 0.5Vcc, the gate output changes. Now the other end of R2 is at approx. Vcc and increases the C1 charging current.

The effect is this: At the very first instant that the B output goes high (on some combination of the real input signal plus noise), it and yanks its own input up higher, so a little negative-going noise on the input no longer is enough to drive the output back low.

Note: R2 has the effect of decreasing the charging rate of C1. To get the same delay time as in the original post, R1, C1, or both can be reduced.

UPDATE: Corrected D1 on the schematic.

enter image description here

\$\endgroup\$
5
  • \$\begingroup\$ This looks great. I mostly follow it. For the quick discharge of C1, should D1 be reversed? And for the hysteresis added by R2, could you help educate me on that? I don't see how that works, and if you could point me to a resource that I could learn from, I'd appreciate it. \$\endgroup\$ – matth Mar 5 at 18:14
  • \$\begingroup\$ Yes, D1 should be reversed. That is a carryover from the first schematic where the input gate is inverting. oops. \$\endgroup\$ – AnalogKid Mar 5 at 18:22
  • \$\begingroup\$ Excellent, thanks. And I found this link which has a pretty good description of how R2 adds hysteresis. ti.com/lit/tidu020 \$\endgroup\$ – matth Mar 5 at 18:41
  • \$\begingroup\$ Updated the answer to include an explanation of hysteresis. \$\endgroup\$ – AnalogKid Mar 5 at 18:43
  • \$\begingroup\$ Perfect, very intuitive explanation \$\endgroup\$ – matth Mar 5 at 18:49

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.