Simpler delay before power on

Question

I'm trying to create a circuit that will make the output go high some amount of time after a 5V control signal goes high. That delay time may vary by application, so I'll use a potentiometer in place of the 249k resistor. I'm thinking of using a 555 timer in monostable with a 5V power supply. Below is the circuit I came up with, and I think it will work, it just seems like I might be coming up with something that's overly complicated because I'm a n00b. Is this a good approach, or is there a simpler/more effective way to do it?

EDIT: One other requirement that I neglected to mention. I want the delayed output to go high after some time, but I also want it to go back low immediately after the input goes low. I feel like that might cause a problem with using an RC filter.

Answer 1

A problem with the 555 in your application is that the 555 was designed from the ground up to use a capacitor that is charged from ground up. To do what you want requires at least one external inverting, device, like a transistor or logic gate.

An alternative is a delay generator made with the gates of a CD4093 quad NAND Schmitt trigger gate. Using a Schmitt trigger gate eliminates a noise burst that is almost guaranteed by the very slow risetime of the large R-C network.

When the input goes from low to high, the output goes from low to high after an R-C delay. When the input returns low, the output goes low immediately. If the time between activations is longer than the delay time, then the circuit will recover nicely. If the time between activations is less than the delay time, adding diode D1 resets the timing capacitor much more quickly.

First pass at a schematic:

UPDATE: This also can be done with three sections of an AND gate, plus one resistor to create a bit of hysteresis.

Answer 2

If your delayed signal feed some TTL logic which has 2.5V treshold, then just use circuit like this. The delay is time until cap gets charged to 2.5V.

The disadvantage is that the delayed signal stays ON for a same while after controll signal gets OFF. Also consider if controll signal is strong enough to charge cap thru 10k without affecting it.

Answer 3

Here is another version of a signal delay circuit. This one uses only three gates. Another possible advantage is that it powers up in the waiting-for-activation state. That is, the initial output state is low if the input is high at power-up. With the other circuit, if the input is high at power-up the output goes high immediately.

U2C is unused. R2 is added to create hysteresis at the U2B inputs. This prevents a U2B output noise burst as its input voltage increases slowly through its transition region.

When the input goes high, U2A pin3 goes high. But C1 is still discharged so U2B pin 4 is still low. R1 and R2 form a voltage divider between the high and low outputs, and the centerpoint voltage is what charges C1. With the values shown, the max voltage across C1 is 0.8 x Vcc, which is greater than the gate's input transition voltage of approx. 0.5 x Vcc. When the capacitor voltage crosses above approx 0.5Vcc, the gate output changes. Now the other end of R2 is at approx. Vcc and increases the C1 charging current.

The effect is this: At the very first instant that the B output goes high (on some combination of the real input signal plus noise), it and yanks its own input up higher, so a little negative-going noise on the input no longer is enough to drive the output back low.

Note: R2 has the effect of decreasing the charging rate of C1. To get the same delay time as in the original post, R1, C1, or both can be reduced.

UPDATE: Corrected D1 on the schematic.