Good evening, I'm having some issues with some verilog code, or quiet a lot to be honest. Or with Lattice's software actually.. This was tried in Lattice Radiant. First off, I'm getting these warnings(I know they're called 'error' I moved their severity up to make them stand out more). The other 106 errors are related to the .ldc file statements and some severity list statements missing

First bunch of errors

but when viewing the netlist analyzer they all seem to be connected. Netlist analyzer

In the Device Constraint Editor they'll show up as unconnected and I cant assign any pin locations to VSync_In and HSync_In. Device Contraint Editor It's programmed in lattice Radiant, with atom as the text editor, the selected FPGA is the UP5k-SG48(ice40 board) and the verilog version is 2001. I tried; adding the complete pin declaration in the module definition, removing the 'wire' statements, going with different names and more things I can't remember anymore. But alas, nothing worked so far. I included a trimmed version of the code below, I removed all block which aren't related to the pins or only after another module.

// Made by yours truly with the intention of learning Verilog and VHDL
// The idea is to convert the DMG video output to VGA and optionally even CGB video.
module DMGtoVGA(
    // MCLK,

/*  SPI-Flash pinout  */
// output wire spi_sck;       //SPI Slave ClocK
output wire spi_ssn;       //SPI Slave Select Negated
// inout wire spi_cs;         //SPI Chip Select ~duplicate of spi_ssn
// output wire spi_mosi;      //SPI Master out, Slave in
// input wire spi_miso;       //SPI Master in, Slave out
assign spi_ssn = 1'b1 ;                   // Disable SPI Flash after configuration

// input wire   MCLK;
input wire RST;
input wire BTN_Down;
input wire BTN_Up;
input wire EN;
input wire HSync_In;
input wire DMG_CLK;
input wire VSync_In;
input wire [1:0] Data_In;
output wire Vsync_Out;
output wire Hsync_Out;
output wire [3:0] B;
output wire [3:0] G;
output wire [3:0] R;

wire    Frame_Sync;
wire    VGA_CLK;     //40MHz VGA pixel clock
wire    CLK_HF;      //internal oscillator output(48MHz)
wire    CLK3DIV;     //Custom devision of the internal HF oscillator
wire    [0:4]PSMode; //pallete selection control input

//Button debouncing
wire Deb_Up, Deb_Down;
Up_deb1 (
  .FILTERIN  (BTN_Up),  // I
  .FILTEROUT (Deb_Up)   // O
Down_deb1 (
  .FILTERIN  (BTN_Down),  // I
  .FILTEROUT (Deb_Down)   // O

//Pallete selection
PalleteSelector PS_inst(

    wire [15:0]DMG_PixelData;
    wire [15:0]VGA_PixelData;
    wire [13:0]VGA_PixelADDR;
    wire [13:0]DMG_PixelADDR;
    wire RAMRDWR_1;
//Decode the DMG input to synced Pixel_Data, any custom pallettes are applied here
DMG_Decoder DMG1_inst(

//PSRAM buffer between VGA and input, should be big enough even for the CGB ':)
//for now only 1x 256Kb bank(32KB is needed)

SP256K SPRAM_inst1 (
  .AD       ((RAMRDWR_1) ? DMG_PixelADDR : VGA_PixelADDR),  // I
  .DI       (DMG_PixelData),  // I
  .MASKWE   (4'b1111),  // I
  .WE       (RAMRDWR_1),  // I
  .CS       (1'b1),  // I
  .CK       (CLK3DIV),  // I
  .STDBY    (1'b0),  // I
  .SLEEP    (1'b0),  // I
  .PWROFF_N (RST),  // I
  .DO       (VGA_PixelData)   // O


Lol, and this isn't even everything. Apparently, the SPRAM module doesn't want to be initialized. But that can wait, I've been at this for a whole week now and it's getting annoying.

  • 3
    \$\begingroup\$ Case sensitive -> HSync_In != Hsync_In. The synthesis errors use the latter, but your code seems to be the former. \$\endgroup\$ – Tom Carpenter Mar 4 at 19:46
  • \$\begingroup\$ @TomCarpenter welp, that's half of the errors gone. I checked if I used the same word everywhere but didn't press 'match case'. Thanks! \$\endgroup\$ – DerekLF Mar 4 at 19:49
  • \$\begingroup\$ Another possible cause is incorrect or incomplete internal blocks which synthesis can optimise away to nothing (leaving the I/Os floating). That's why you get it working in simulation first... \$\endgroup\$ – user_1818839 Mar 4 at 22:43
  • \$\begingroup\$ @BrianDrummond I haven't check if they show up connected in the Sub-RTL. So I'll check that when I'm home \$\endgroup\$ – DerekLF Mar 5 at 15:18


After diving deeper in the RTL, I noticed some data lines were unconnected even though they were used in the code. So I can't explain what happened there, but I divided the code into 3 separate processes. And now they show up as connected, and even the SRAM module is being initialized.

I do want to find out why the synthesis ignored that code, but that's unrelated to the question. So I'll open a topic for that some other day, if I can't figure it out.

  • \$\begingroup\$ DerekLF - Hi, Thanks for coming back with an answer to your question. If, as I think you are saying, you are not looking for further help on this question, then please "accept" your answer, to denote the topic as solved (i.e. click the "tick mark", so it becomes green). That avoids the site nagging us in future, about this question not having an accepted answer. Thanks. \$\endgroup\$ – SamGibson Mar 6 at 20:12

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