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I am attempting to connect a CMOS parallel SRAM chip to a few different 74HC chips, but mostly 74HC377 octal flip-flops.

I'm having inconsistent results with values being loaded sometimes not being correct. Looking at the data sheet, the 74HC377 has a high level input of 3.15V with Vcc at 4.5 volts, and the SRAM has a minimum high level output of 2.4V at the minimum Vcc, which is 4.5V. In my measurements, the SRAM high output is around 3.5 volts, and as Vcc is around 5.2 volts it's probably just barely enough to register as high to the 377, which explains the instability.

Why the heck is the SRAM high level output not just Vcc like everything else? I've looked for other SRAM chips that have compatible voltages but it seems like they all have this. What can be done to accommodate this? Or am I doing something wrong?

Edit: the SRAM chip is a Renesas 71256SA, and I measured the voltage using a multimeter.

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  • \$\begingroup\$ Might help if you state the sram part number and how you’re measuring the voltages. \$\endgroup\$
    – Kartman
    Mar 5, 2021 at 2:30
  • \$\begingroup\$ I’d be using an oscilloscope to measure the active voltages. If you’re using a multimeter then I’m assuming the address and control pins are static and that the chip is selected and the output enabled. Otherwise you’ll be measuring leakage. Also note the ram chip is very fast , so the 0V and bypassing will be critical. This alone could explain your problems. \$\endgroup\$
    – Kartman
    Mar 5, 2021 at 3:13
  • \$\begingroup\$ I don't have an oscilloscope so there's that, but the address and control pins are static and correct. Could you explain what bypassing is and why it's critical? I'm a noob. \$\endgroup\$
    – bobbbob
    Mar 5, 2021 at 3:20
  • \$\begingroup\$ Is it the same as a decoupling capacitor? Because I do have that. What about the 0V is critical though? \$\endgroup\$
    – bobbbob
    Mar 5, 2021 at 3:27
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    \$\begingroup\$ You need a 74HCT377 from the HCT series devices to interface with TTL. \$\endgroup\$ Mar 5, 2021 at 3:36

1 Answer 1

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Presumably the SRAM is using two N channel transistors for driving the output pins.

link

enter image description here

This provides more drive current than a P channel FET of the same size with the small disadvantage of dropping 1x the threshold voltage. For TTL this doesn't matter since TTL only requires Vh to be above 2 volts or so. This is a problem for CMOS inputs though which expect Vh to be higher.

There's a few possible solutions:

You could use 74HCT rather than 74HC chips. These have TTL compatible inputs that treat everything above 2V as logic high. Only chips that use the data line values as input must be HCT series since their outputs are CMOS compatible. Everything else can be normal 74HC series.

You could add pull up resistors to the data lines. 1K resistors are supposed to work reasonably well though this depends on fan out and operating frequency.

enter image description here

If you're really lazy, considering your circuit is somewhat stable already, just drop the logic supply voltage by half a volt with a diode. The 74HC series logic works down to 2V so 4.5V is not a problem. You don't have to do this for all the logic, just the chips that directly interface with the SRAM. Those ones will now have a lower threshold for Vih and output 4.5V as their Voh which everything else directly powered by the 5V rail will accept without problems. Half a volt will probably get you to stability and this saves having to add the resistors at least during prototyping. Just replace the jumper wire powering the octal flip flop with a diode.

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  • \$\begingroup\$ Would using a pull up resistor on the bidirectional I/O of the SRAM cause problems when data is output from CMOS to the SRAM? \$\endgroup\$
    – bobbbob
    Mar 5, 2021 at 18:06
  • \$\begingroup\$ As long as whatever is driving that node can pull the node down to an acceptable voltage for the logic, no. If you use a 1K pull up resistor, whatever drives the node low has to sink 5mA at an acceptable Vil for the SRAM. Datasheet for the SRAM says 0.8V guarantees low won't be misinterpreted as high. The general datasheet for 74HC IO characteristics suggests this is fine cl.cam.ac.uk/teaching/2003/DigElec/part2-data.pdf . Vol @Isink=4ma is typically 150mV(260mV worst case). That should meet the 0.8V requirement at 5v and doesn't dissipate much power in the 74HC IC itself. \$\endgroup\$ Mar 5, 2021 at 20:38
  • \$\begingroup\$ The resistor method fixed the problem. I did some calculations and I think the voltage should be around 2.6V to register as high at my Vin, so I used a 440ohm resistor instead. The 1K didn't work. \$\endgroup\$
    – bobbbob
    Mar 8, 2021 at 22:46

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