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I have an example program compiled for the ATSAML21E18B, which uses an M0+. The project was generated using the default Atmel START settings for this device. I initially uploaded the .bin to the device using JLink's software, the command is as follows:

loadfile /home/azimuth/example-l21/gcc/AtmelStart.bin,0

Stepping through this shows two LDR instructions executing successfully, and then a PUSH which causes a HardFaultMemManage, causing the device to interrupt into an exception handler where it hangs on an infinite loop. The offending instruction is on line 453 here. The fault jumps to the "Dummy Handler" directly above on line 445.

https://pastebin.com/08uENS29

I am lost as to why this exception can occur here, the stack pointer is pointing safely into SRAM as shown by the value of SP below. My initial suspicion was that I was perhaps loading the .bin to the wrong address, but everything ive seen of this upload method shows images being uploaded at address 0.

J-Link>r
Reset delay: 0 ms
Reset type NORMAL: Resets core & peripherals via SYSRESETREQ & VECTRESET bit.
J-Link>s
00000240:  11 48              LDR       R0, [PC, #+0x44]
J-Link>s
00000242:  12 49              LDR       R1, [PC, #+0x48]
J-Link>regs
PC = 00000244, CycleCnt = 00000004
R0 = 00000324, R1 = 20000000, R2 = 3F3D0002, R3 = 86082820
R4 = 58617C18, R5 = 25D4819D, R6 = 02D6011D, R7 = 513170AB
R8 = 7F081161, R9 = 431A11A1, R10= 43910040, R11= 08A04DB3
R12= 41801210
SP(R13)= 20002020, MSP= 20002020, PSP= 98216104, R14(LR) = FFFFFFF9
XPSR = 11000000: APSR = nzcVq, EPSR = 01000000, IPSR = 000 (NoException)
CFBP = 00000000, CONTROL = 00, FAULTMASK = 00, BASEPRI = 00, PRIMASK = 00
FPU regs: FPU not enabled / not implemented on connected CPU.

The second output is the regs after the exception has occurred.

J-Link>s
00000244:  70 B5              PUSH      {R4-R6,LR}
J-Link>regs
PC = 0000023C, CycleCnt = 00000000
R0 = 00000324, R1 = 20000000, R2 = 3F3D0002, R3 = 86082820
R4 = 58617C18, R5 = 25D4819D, R6 = 02D6011D, R7 = 513170AB
R8 = 7F081161, R9 = 431A11A1, R10= 43910040, R11= 08A04DB3
R12= 41801210
SP(R13)= 20002000, MSP= 20002000, PSP= 98216104, R14(LR) = FFFFFFF9
XPSR = 11000003: APSR = nzcVq, EPSR = 01000000, IPSR = 003 (HardFaultMemManage)
CFBP = 00000000, CONTROL = 00, FAULTMASK = 00, BASEPRI = 00, PRIMASK = 00
FPU regs: FPU not enabled / not implemented on connected CPU.
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    \$\begingroup\$ Could you please replace the images by copy-pasted content in a block code element? This is very hard to read on mobile and not accessible. \$\endgroup\$
    – jaskij
    Mar 5, 2021 at 9:36

1 Answer 1

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I have determined the issue, I incorrectly specified the *E18B version of the device when I was in fact programming an *E15B. The SRAM sizes differ, meaning that my stack was located at an illegal address. I determined this by the simple expedient of looking at the chip.

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