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I am trying to design a CAN bus expander. In this case I could implement star topology of multiple buses in parallel. It would avoid having problems with reflections and delay.

For this purpose I prepared a simple schematics, that basically reflects RX signal from the CAN transceiver to the open-drain bus and then connects it to other RX and TX pins of other transceivers. My understanding is that this should work with CAN bus, keeping in mind dominant bits have priority.

The only question remains: Is it OK to connect RX via open-drain circuit to TX of the same bus? I would say it is, but this is the part I am asking actually.

My circuit (drawn on tablet) enter image description here

Image shows 3 different CAN transceivers connected in parallel. No matter on which bus signal is received, other 2 should see the same on their output.

This is schematics that works (verified), which I try to optimize. You can connect as many blocks as you want. enter image description here

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  • \$\begingroup\$ You would have to know which CAN tranveiver it is and read the datasheet of it to anwer this. \$\endgroup\$
    – Justme
    Mar 6, 2021 at 13:19
  • \$\begingroup\$ Why? CanH and CanL are standardized, so is TX and RX output. Taking into account speed (if neceaaary), it is 125kbit. Im using TJA1050 otherwise. \$\endgroup\$ Mar 6, 2021 at 13:21

2 Answers 2

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The TJA1050 CAN PHY can't be used to make a passive CAN hub/repeater.

If any device starts to pull the TXD is low to transmit dominant state on the CAN bus, the receiver is still active as it can monitor for collisions so it will soon after pull RXD low, which in turn will keep your TXD low and so the state latches low. At some point the PHY transmit timeout will activate and maybe release the RXD high. But you have three chips with all RXDs being able to drive the TXDs.

Most likely need an MCU with three CAN controllers to handle three CAN bus segments, and a microcontroller to forward messages between them.

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  • \$\begingroup\$ There is no MCU on right side. So any transaction is initiated by RX pin only. Does it still apply? \$\endgroup\$ Mar 6, 2021 at 19:12
  • \$\begingroup\$ Yes. If any bus goes to dominant state, it's RXD goes low, it pulls all TXDs low, all buses go to dominant state, all RXDs are low, they all keep TXDs low. \$\endgroup\$
    – Justme
    Mar 6, 2021 at 19:29
  • \$\begingroup\$ Ive updated my question with working circuitry that certainly works but Im having difficulties to properly understand it and look for alternate solution. \$\endgroup\$ Mar 7, 2021 at 11:47
  • \$\begingroup\$ That circuit works because it has logic circuitry to prevent the lockup. Your original schematic didn't so it will end up having the lockup. \$\endgroup\$
    – Justme
    Mar 7, 2021 at 12:07
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There is/was a chip available that did the job of dealing with 1+2 CAN channels very well. It is the AMIS42700, which was discontinued. I have seen the above gate version with no need of an CPU. Looks great. There is a very similar design on the web from Otmar Schmid at oschmid.ch.

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    \$\begingroup\$ InSearch - Hi, Stack Exchange rules mean that you cannot ask a new question in something posted as an answer. Therefore that part has been removed from your post. The website you mentioned seems to have only a blank "holding page" for any of the links related to CAN bus, Therefore it isn't clear what you are referring to. In general, we want to have self-contained answers on Stack Exchange, so in case a referenced linked site goes down, there should be enough information in an answer to still answer the original question. More site rules in the tour & help center. Thanks. \$\endgroup\$
    – SamGibson
    Oct 27, 2022 at 11:24
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    \$\begingroup\$ If you want to ask a related question, please read the tour & help center first, then ask a new question. Make sure it is on-topic, include all relevant details, known constraints, schematics etc. and include a link to this question above, if it is relevant (and explain how your question differs from it). Thanks. \$\endgroup\$
    – SamGibson
    Oct 27, 2022 at 11:43

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