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I need some hints in designing a ±300 V amplifier stage. The output stage should be two MOSFETs. The current needs to be very low for now (about 50 mA). The bandwidth is not so important for now.

The problem with this is that I cannot apply any standard circuit like a discrete operational amplifier because of the voltage and it is hard to get good BJTs for that voltage range to drive the complementary MOSFETs.

What I want to achieve is a gain of 40, to be able to control the output voltage with a generated input voltage from a controller. Do you have any literature hints for me especially for high voltage amplifiers?

Now I simulated some very basic operational amplifiers. This is a very simple one with resistors as current source but it works in the DC simulation. It is not fast at all. The downside is that there is a lot of offset which must be corrected at the input of X5. The voltage range is also limited because the choice of transistors requires these low voltages. Maybe I could scale that up to 200V for each rail. What do you think? Is this a design to refine for a very simple voltage source or are there design issues one can't solve in a real world application?

enter image description here

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    \$\begingroup\$ what sort of amplifier? Class D? A? And what type of mosfets are you using? \$\endgroup\$
    – Kartman
    Mar 6 at 15:02
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    \$\begingroup\$ I use IXTH24N50L and IXTH10P60. The sort of amplifier should be linear class AB but not switched. \$\endgroup\$
    – Gustavo
    Mar 6 at 15:04
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    \$\begingroup\$ Power mosfets are used for switching. They don't have a useful linear region of operation. \$\endgroup\$
    – Kartman
    Mar 6 at 15:08
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    \$\begingroup\$ They don't have a useful linear region of operation In a common source configuration, I would agree that that would be a challenge. However power MOSFETs are very usable in the common drain configuration (source follower), for example: redcircuits.com/Page175.htm And residual distortion can be lowered by using feedback (you would use feedback for any decent amplifier of course). \$\endgroup\$ Mar 6 at 15:23
  • \$\begingroup\$ I need some hints in designing a ±300 V amplifier stage. Hmm, suppose that wasn't +/- 300 V but instead it was ±30 V, would you still need hints? Just trying to get an idea of your skill level. I have over 25 years of experience in designing low voltage circuits but still I consider ±300 V a challenge. \$\endgroup\$ Mar 6 at 15:27
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For +/- 300V output, you'll need supplies a bit above that to account for drive voltage requirements, and a bit of margin. Personally I'd use +/-325V DC power supplies since that's the rectified output of a cheap 1:1 mains isolation transformer running on 230V, so you don't have to visit the audiophile shop for a gold-plated, custom tube amp transformer. This is obviously a lethal project, don't sue me.

So, 650V transistors (or a bit more) would be desirable, with a package that can dissipate the required power, and an appropriate SOA.

There are no PNP BJTs that fit the bill on Mouser. There are a few NPNs, but at this high voltage you get SOA problems due to second breakdown. This is FJL6920TU, a TO-247, 20 Amp NPN, and the current its SOA allows at 600V is really tiny.

enter image description here

So it will either have to be a kludge with cascodes, or FETs. PMOS stop at 600V, and there are a few 600V PMOS that would be suitable if you wanted an output of, say, +/-275V, but for +/-300V that won't work.

So, with the PMOS choice narrowed down to "none", it'll have to be a N-channel job.

You could get away with a TO-220 package but you say "The current needs to be very low for now (about 50 mA)" so, when I read "for now" I just feel it coming: "now that it works how do I get 200mA?"... so let's overdesign it a bit and use TO-247 or TO-3P FETs. Note the whole point of these big packages in this design is to have more thermal interface material area on the back so thermal resistance to heatsink is lower, so when an regrettable event happens like a short on the output, the FET chip has more thermal margin before it blows. Larger thermal mass due to the huge copper slug on the back also helps.

When picking a FET for linear use, the first thing to check is it actually allows linear use, which should be mentioned in the datasheet. Next check that the SOA graph has a curve for "DC" and it is a straight line, without a second higher slope at high voltage that looks like a BJT second breakdown.

FQA6N90C looks good, 900V 6A, and RthJC of 0.63°C/W. Also this QFET series are popular in linear applications, look at that beautiful DC Safe Operating Area, constant power at DC, and your short circuit protection will be easy to design.

enter image description here

If you get a lower current FET in an attempt to get lower capacitance then it will have a smaller chip and thus a higher RthJC so it will run hotter and have a smaller SOA.

This is a FET that is NO GOOD for linear use, notice the much higher slope in the SOA:

enter image description here

You can use a SiC FET too, if you want sexy.

Now, driving transistors. PNPs also stop at 600V, which means the VAS transistor of the amp will have to be NPN, or even NFET. As for the current source at the top, you want DC so it can't be a bootstrap. DN2470 depletion FET will work fine, at 1mA it will stay cool. I was also tempted to use a combo of a photocell isolator for a local isolated gate drive power supply, plus a transformer for the AC part of the gate drive, but that would be slight over-engineering.

So. No semiconductors of the P gender easily available above 600V, which means...

enter image description here

I've used 250V rails because I don't have spice models for the higher voltage FETs.

On the left we have a classic input stage. If we slap the full 300V on the input transistors, then any slight variation of their current will create a large variation in dissipation, and thus a thermal DC offset, and a long settling time to DC. Thus, Q2,Q3 are cascodes. Pick a 400V PNP that is suitable for cascode job (ie, low capacitance).

Q4 Q5 Q6 Q7 can be matched pairs, like BCM850/860, these are cheap.

If there is too much offset variation due to self-heating in the input stage, you can wire the amplifier in inverting mode which will keep the input stage Vce constant, and switch the cascode base voltage to minus a few volts instead of -12V.

X5 is the VAS transistor. I picked a FET because it has high open loop gain at DC, and its SOA is also nice. You can use a 700V NPN but if you want a SOA larger than one milliamp at 600V then you'll have to pick a pretty large, low hFe transistor which means it will need a darlington to have enough gain. Or you can cascode it.

D1 protects the FET gate against overvoltage on negative clipping. R20 protects it against overcurrent. If you use BJTs instead, drop the zener and the resistor and put a Baker clamp diode between B and C. And double check the SOA.

M4 is a DN2470 wired as 1mA current source. I used DN2540 spice model which is wrong, so the resistor value is also wrong.

X2 and X3 are FQA24N50 FETs that are only rated to 500V but I had the model. Use 900V FQA6N90C instead. It should be faster.

X3 is our single-ended drive transistor. D2 protects its gate against overvoltage (both positive and negative) and Q8 protects against overcurrent. Set R19 to a suitable value, Imax = Vbe/R19.

C3+R18 is a zobel for stability, may not be necessary.

X2, Q1 make the current source to bias it in single ended class A. Zener D3 is required to protect the gate from overvoltage on negative clipping. Idle current is Vbe/R6, here 50mA.

With a single-ended class A amp you waste power but there is no need for bias temperature compensation, as would be the case with a push pull. And we can't have a push pull anyway because no PMOS.

C1 C2 R15 are the compensation network, adjust to taste for proper phase margin.

It needs quite a bit of positive headroom due to M4/X3.

Performance is... actually not that bad. You get 2V/µs slew rate and a bandwidth up to about 100 kHz. That's with the wrong spice models, of course. Clipping behavior is pretty sticky, but that shouldn't be a problem in your use case.

Here's another version, that might actually be better. The bottom power transistor is used as VAS and output, directly driven from the input stage. The top one is now the single-ended current source. This time I used output-inclusive compensation, which is a bit risky, but you should adjust the compensation with real transistors anyway, not my wrong spice models. It also depends on the load, notably cable capacitance, and whether you put a zobel on the output to protect against that.

enter image description here

Now, you may ask, "I don't want single ended class A, I'm not audiophile". Okay...

EDIT: improved

enter image description here

So, no PNP, except if we put them in a position where they can be low voltage, for example in the low voltage local power supply created by zener D4.

In this version, when current through the bottom FET gets a bit low Q11 turns off and via current mirror with gain Q14 Q15, increases the current of the top FET. So, the bottom FET drives the top FET, but since the bottom FET never turns off it stays in control of open loop gain, which means we don't have two different open loop gains and stability conditions depending which FET is actually on, which would be... complicated. Q12 must use a tiny current so it doesn't run out of SOA, hence the current mirror with gain on top. This shows pretty good slew rate and settling, and it will do a lot more current than you need with low idle dissipation, but values of R20-22 need to be just right.

C1 should probably be higher, like 100pF.

Since you have a resistive load, another way to increase available current without a push pull, while keeping the Q8/X3 current source, is to add resistors R22/R23 to tweak Q8 base voltage, which increases current in FET X3 when output voltage increases towards the positive rail. Adjust resistor values to get the current you need. This is just the upper right part of the schematic, and the only change is the two resistors R22 R23.

enter image description here

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  • \$\begingroup\$ This is so much work you put in to explain that. Thanks. I tried simulating your second circuit which is a clean design but the problem with my simulation is that i the output does not go down to the negative rails but stays at 140V when the input voltage is negative. I designed to have a gain of 50 \$\endgroup\$
    – Gustavo
    Mar 9 at 17:00
  • \$\begingroup\$ And just out of ciriosity: The design seems to be very seusceptible to unequal rails is that right? \$\endgroup\$
    – Gustavo
    Mar 9 at 17:53
  • \$\begingroup\$ It was a fun challenge ;) Now I just tested with unequal rails and it works well, so I think you might have either a schematic error or a wrong spice model \$\endgroup\$
    – bobflux
    Mar 9 at 18:26
  • \$\begingroup\$ I've noticed that my sim does model MOSFET breaking down when voltage rating is exceeded, so I was not able to cheat and use the lower voltage spice models that I had on hand with the high voltage supply... had to use suitable supply voltage for the models. \$\endgroup\$
    – bobflux
    Mar 9 at 18:26
  • \$\begingroup\$ I noticed that one of my BJT models was wrong. The supplied models hat a diode in it which caused a lot of trouble. I wonder one thing in the second circuit. M4 and R16 build a current source but it is actually directly connected to the gate of X3. In the first circuit I completely understand that X5 and M4 build a voltage amplification. \$\endgroup\$
    – Gustavo
    Mar 10 at 7:34
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What I need it for is VI measurement in plasma. The input is a voltage ramp which should result in a amplified voltage ramp at the output.

Simplest option: drive the plasma with the output of a step-up transformer connected to an audio amplifier that outputs a clean 50Hz sine. Measure current and voltage. Accuracy of results will depend on how it reacts to AC though, and may depend on frequency.

Now, with a current source. Instead of setting voltage and measuring current, it's much simpler to set current and measure voltage.

enter image description here

Adjust 1R resistor to something like 100R to have a 0-50mA range with 0-5V input. Pick a low offset opamp, and a >350V linear MOSFET, for example from the FQA QMOS range from OnSemi ex-Fairchild.

Add a DPDT relay to reverse the polarity of the load for measuring current in both directions.

Measure voltage across your plasma with a differential probe.

Another, even simpler method:

enter image description here

Close switch, wait until capacitor is charged to +300V. Open switch. Measure V and I as capacitor discharge. The DMOS acting as current sink provides an additional current to discharge the cap near 0V. Then flip the polarity of the plasma with relays and do it again the other way around.

Here's another one, bipolar this time.

enter image description here

Close the switch to charge C2 then open it. Constant current source around X4 makes a ramp ; X3 is used as voltage follower ; X2 is another constant current source to bias it. This makes it a class-A amp, but that's not a problem here. Acquire output voltage and current and you get your I-V.

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  • \$\begingroup\$ Thanks for the advive. Unfortunately I need voltage control mode to track potential of the plasma so the only option is to use a voltage controlled voltage source for that. Also I need precise start and stop point and not just a ramp from upper rail to lower rail. \$\endgroup\$
    – Gustavo
    Mar 8 at 15:50
  • \$\begingroup\$ OK, I will make another answer XD \$\endgroup\$
    – bobflux
    Mar 8 at 17:37

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