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I'm reading the datasheet of MAX5725 but I cannot understand which SPI mode it uses. At page 18 I read:

[...] the data is shifted in synchronously and latched into the input register on each falling edge of the serial clock input (SCLK).

This limits the SPI mode to 1 (clock idle low, sampling on second edge) or 2 (clock idle high, sampling on first edge).

I also looked at Figure 1 where there are the SPI signals, but unfortunately it's not so clear the idle state of the clock signal. Following this figure both modes would fit.

From which other parameter should I understand the actual SPI mode it uses?

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It can use either mode. When writing to the chip, it does not matter if clock idles low or high, the falling edges still load data in. For reading, the chip allows you to specify which clock edge you want to use for reading.

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