Why for setup check AND gates use rising edge, while OR gates use falling edge and vice versa for hold check in clock gating?

Question

I have two questions on set_clock_gating_check SDC command.

1. Why for setup check, AND, NAND gates use rising edge, while OR, NOR gates use falling edge ?

2. Why for hold check, AND, NAND gate use falling edge, while OR, NOR gates use rising edge ?

Answer 1

For AND and NAND gate, the output is known if any one of the inputs is 0. So the input that is 0 can be said to control the output, and that input can be said to be non-controlling if it changes to 1. So rising edge of the clock changes the clock signal from controlling input to non-controlling input. Setup check is the duration for the inputs to remain stable before the active edge of the clock, while hold check is the duration for which the inputs have to remain stable after the active edge of the clock. Here we can consider that when the clock signal is 0, it controls the AND/NAND Gate, and when it is 1, the control goes to other inputs. So when the clock is 1 it can be said to enable the AND/NAND gate. When clock is 0 it can be said that the AND/NAND gate is disabled. So for setup check we consider the rising edge of the clock. For hold check we consider the duration for which the inputs have to be stable when the gate is disabled, and this occurs on the falling edge of the clock for the AND/NAND gate.

Similarly for NOR and OR gate the output is known if any one of the inputs is 1.