How to view the internal signals of module in ModelSim using the testbench?

I have looked over this tutorial (Tutorial - Using Modelsim for Simulation, for Beginners. ) how to add waves and write test benches for VHDL module

I looked over some answers as well like this one to find out but I could not use it.

Quartus, Modelsim, VHDL - Viewing Internal Signals

Now, if I want to add some internal signals and view them, how can I do since I am using the vhdl code as components in the testbench?

and to clarify it well, here is the code of the module:

 library ieee;
use ieee.std_logic_1164.all;

entity and_gate is
port (
input_1    : in  std_logic;
input_2    : in  std_logic;
and_result : out std_logic
);
end and_gate;

architecture rtl of and_gate is
signal and_gate : std_logic;
signal not_and  : std_logic;
begin
and_gate   <= input_1 or input_2;
and_result <= and_gate;
not_and    <= not and_gate;
end rtl;


and here is the code of testbench library ieee; use ieee.std_logic_1164.all;

 entity and_gate_tb is
end and_gate_tb;

architecture behave of and_gate_tb is
signal r_SIG1   : std_logic := '0';
signal r_SIG2   : std_logic := '0';
signal w_RESULT : std_logic;

component and_gate is
port (
input_1    : in  std_logic;
input_2    : in  std_logic;
and_result : out std_logic);
end component and_gate;

begin

and_gate_INST : and_gate
port map (
input_1    => r_SIG1,
input_2    => r_SIG2,
and_result => w_RESULT
);

process is
begin
r_SIG1 <= '0';
r_SIG2 <= '0';
wait for 10 ns;
r_SIG1 <= '0';
r_SIG2 <= '1';
wait for 10 ns;
r_SIG1 <= '1';
r_SIG2 <= '0';
wait for 10 ns;
r_SIG1 <= '1';
r_SIG2 <= '1';
wait for 10 ns;
end process;

end behave;


and here are my signals are all went to red eventhou I added their waves:

• What exactly you didn't understand from Quartus, Modelsim, VHDL - Viewing Internal Signals ? It clearly shows how to add internal signals. Mar 8, 2021 at 20:37
• I updated my question. I did not understand how to add waves from vhdl code even though I added them as you see in the updated question Mar 8, 2021 at 21:22
• @Yaakov I wasn't able to reproduce your problem. The simulation gives me proper results and shows all internal signals. I had to complete the code of the testbench though: add libraries, entity and architecture declarations. I am not sure what the problem may be. Btw, you have a funny name for OR logic. Mar 9, 2021 at 6:46
• The code was mainly made for AND logic and I wanted just to check if I change the code,the waveform changes too. What can go wrong in my testbench code then? Mar 9, 2021 at 6:55
• @Yaakov I have posted an answer, hope it helps. Let me know, if you need to see my testbench code. Mar 9, 2021 at 6:57

Basically, you can add any signal in your project to a waveform to simulate. After creating Simulation Configuration you double click on it in a Project tab, which should get you to the sim tab. You will see the hierarchy of your project there. By clicking on the name of the entity under test, you will be able to see its internal signals in the Objects tab. Then you just right click the desired signals and choose Add Wave.
• I'm glad, that it helped. There is a View menu, where you can select Project by clicking or pressing x. Mar 9, 2021 at 7:25