I've been tasked with massivly expanding some GPIO of a microcontroller, and my inital thought was to chain a bunch of SN74HC595 and SN74HC597 shift registers, however to get the ammount that's required I'm looking at 32x PISO and 32x SIPO shift registers. This seems like a lot and I'm concerned about a few things....
Would the 25mA Sink/Source of my Micocontroller be enough to drive all 32x clocks/latches/resets..etc? If not, could I use a number of buffers to drive blocks of 8x shift registers in parallel? Such as below?
I'm assuming as long as the shifting/clocking of data through the chain isn't too fast I can limit the effects of propergation delays?
Anything I've missed that I should be worried about? It seems wacky but in principle ok? Any particular design or layout considerations?