0
\$\begingroup\$

I am using an A7-100T FPGA development board used for a project. Up to this point, I have only been doing simulations on Vivado with simulated clocks or when I have been using the board, I have not had to create any clock signals due to only having basic combinational logic designs.

What is the simplest way to create clock signals? I have read tutorials and watched videos and it seems you have to create an IP package and use the HDL code as a component within the top-level file on the design?

I need to produce two clock signals at the same frequency with one of them having a 90-degree phase shift.

\$\endgroup\$

2 Answers 2

1
\$\begingroup\$

The A7-100T has an on-board clock and the Xilinx XC7A100TCSG324-1 FPGA itself has a very comprehensive clock generation system built-in.

The datasheet: Xilinx 7 Series Datasheet

Highlights it as:

7 Series Clocks 1

7 Series Clocks 2

\$\endgroup\$
5
  • \$\begingroup\$ So I have used the clocking wizard and instantiated the clock component. But what do I input into the component for the clock in? \$\endgroup\$
    – David777
    Mar 9, 2021 at 11:27
  • 1
    \$\begingroup\$ The 7 Series FPGAs don't have a self-generating clock. You, as the designer, must provide an input block that the FPGA's on-board clock circuits can use to generate the specific clocks you need. Check the ARTY-A7's documentation but as I recall there is a single 100 MHz clock that drives the E3 pin on the FPGA. \$\endgroup\$
    – jwh20
    Mar 9, 2021 at 11:58
  • \$\begingroup\$ Sorry for my total lack of knowledge on this, but is this clock then set in Vivado in a constraints file like you would with an input or output pin, and then fed into the clock wizard component? \$\endgroup\$
    – David777
    Mar 9, 2021 at 15:22
  • \$\begingroup\$ @jwh20 they actually do, but it's not very accurate or stable. You can access the ring oscillator used for loading the configuration data using the STARTUP primitive. It can occasionally be useful. \$\endgroup\$ Mar 10, 2021 at 10:09
  • \$\begingroup\$ You need to connect the PLL input to some clock signal. Presumably your FPGA board has an oscillator on it, take a look at the schematic and figure out what the frequency is and what pin it's connected to. You'll also want to tell Vivado about it with the constraints file. Note that the constraints file doesn't actually create the clock, it just tells Vivado to assume that there is an external clock on that pin with the specified period. \$\endgroup\$ Mar 10, 2021 at 10:11
1
\$\begingroup\$

You don't, you have to use an external oscillator of some sort. But once you have that, then you can use a PLL, DCM, or similar FPGA primitive to generate derived clocks at different frequencies and phases. Take a look the documentation for the FPGA board and the FPGA tools that you're using for the specifics. For Vivado, the simplest thing is probably to use the clocking wizard, and that produces a module that you can instantiate and connect the appropriate inputs and outputs.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.