I am using an A7-100T FPGA development board used for a project. Up to this point, I have only been doing simulations on Vivado with simulated clocks or when I have been using the board, I have not had to create any clock signals due to only having basic combinational logic designs.
What is the simplest way to create clock signals? I have read tutorials and watched videos and it seems you have to create an IP package and use the HDL code as a component within the top-level file on the design?
I need to produce two clock signals at the same frequency with one of them having a 90-degree phase shift.