When watching a few videos about stackup, EMI and impedance (especially this video from Fedevel Academy: https://youtu.be/52fxuRGifLU), I got confused how to compute trace impedance in the case of two signal layers between ground planes.
Considering a stackup including at least 4 successive inner layers such as:
- L2: ground (GND)
- L3: Signal layer, it could have no copper pour (option A), ground pour (option B), power pour (option C).
- L4: Signal layer, it could have no copper pour (option A), ground pour (option B), power pour (option C).
- L5: ground (GND)
The stackup is represented below. Some layers exist above L2 and below L5 but are considered out of the scope. Signal traces on L2 and L3 are orthogonal as shown. Distance between layers is assumed to be the same between all these layers.
In the following, we will focus on signal tracks on L3 only.
Option A - without copper pour on L3 and L4. It seems to me that the impedance for L3 traces can be computed using standard calculations for striplines: reference layers for L3 traces are L2 and L5 (reference layers for L4 would be also L2 and L5). Equidistance between layers implies that 80% of the electromagnetic field for signal traces on L3 will be between L2 and L3 since the fields are proportional to the inverse of distance squared. Since signal traces on L3 and L4 are also orthogonal to each other, it should limit cross coupling between signals. This option A seems to be a decent solution to me up to some frequencies as described in this video (reference: https://youtu.be/52fxuRGifLU?t=1774 [29:34])
Option B - With power pour on L3 and L4. This option comes from a 12 layer board stackup suggested by Rick Hartley (reference: similar video to above https://youtu.be/52fxuRGifLU?t=3698 [1:01:38]).I assume that signal traces on L3 can only "see" L2 and L4 (L5 being hidden behind power pour on L4). It seems to me that it does not exist a continuous return path on L4 for L3 traces. Even though L4 is not a continuous plane, should it actually be considered as a solid reference plane when calculating the impedance for L3 traces? Is it possible that L3 is only referencing to L2 which is the lowest impedance path for return current? If so, what to tell the PCB manufacturer for controlled impedance calculations (since striplines are supposed to be between two planes and microstrips on the PCB top or bottom)? Moreover, it is then unclear if the power pour on L4 needs to be power actually used to generate signals on L3 or if it does not matter in that case.
Option C: with ground pour on L3 and L4. I assume that signal traces on L3 can only "see" L2 and L4 again. As for option B, it seems to me that it does not exist a continuous return path on L4 for L3 traces. The current would then go through some ground vias connecting L2 and L3 but that would add quite a bit of inductance for this path... Similarly to option B, can we then consider that the current will follow the path of lowest inductance and flow mostly through L2? If so, how to work with the PCB manufacturer for this design again since it is does not look like microstrip?
- Feel free to comment and discuss any points/questions above. I may misunderstand some basic concepts.
- For option B and C, how does L4 come into play when calculating the trace impedance for L3 traces?
- For option B and C, if L4 cannot be considered as a solid reference plane, what to do to estimate the required trace width for controlled impedance, and how do we work with the PCB manufacturer?
- Does option B have any advantages over option C except that it allows to carry some power "tracks" which may not fit anywhere else in the PCB?
Thank you !