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When watching a few videos about stackup, EMI and impedance (especially this video from Fedevel Academy: https://youtu.be/52fxuRGifLU), I got confused how to compute trace impedance in the case of two signal layers between ground planes.

Considering a stackup including at least 4 successive inner layers such as:

  • L2: ground (GND)
  • L3: Signal layer, it could have no copper pour (option A), ground pour (option B), power pour (option C).
  • L4: Signal layer, it could have no copper pour (option A), ground pour (option B), power pour (option C).
  • L5: ground (GND)

The stackup is represented below. Some layers exist above L2 and below L5 but are considered out of the scope. Signal traces on L2 and L3 are orthogonal as shown. Distance between layers is assumed to be the same between all these layers.

Stackup

In the following, we will focus on signal tracks on L3 only.

Option A - without copper pour on L3 and L4. It seems to me that the impedance for L3 traces can be computed using standard calculations for striplines: reference layers for L3 traces are L2 and L5 (reference layers for L4 would be also L2 and L5). Equidistance between layers implies that 80% of the electromagnetic field for signal traces on L3 will be between L2 and L3 since the fields are proportional to the inverse of distance squared. Since signal traces on L3 and L4 are also orthogonal to each other, it should limit cross coupling between signals. This option A seems to be a decent solution to me up to some frequencies as described in this video (reference: https://youtu.be/52fxuRGifLU?t=1774 [29:34])

Option B - With power pour on L3 and L4. This option comes from a 12 layer board stackup suggested by Rick Hartley (reference: similar video to above https://youtu.be/52fxuRGifLU?t=3698 [1:01:38]).I assume that signal traces on L3 can only "see" L2 and L4 (L5 being hidden behind power pour on L4). It seems to me that it does not exist a continuous return path on L4 for L3 traces. Even though L4 is not a continuous plane, should it actually be considered as a solid reference plane when calculating the impedance for L3 traces? Is it possible that L3 is only referencing to L2 which is the lowest impedance path for return current? If so, what to tell the PCB manufacturer for controlled impedance calculations (since striplines are supposed to be between two planes and microstrips on the PCB top or bottom)? Moreover, it is then unclear if the power pour on L4 needs to be power actually used to generate signals on L3 or if it does not matter in that case.

Option C: with ground pour on L3 and L4. I assume that signal traces on L3 can only "see" L2 and L4 again. As for option B, it seems to me that it does not exist a continuous return path on L4 for L3 traces. The current would then go through some ground vias connecting L2 and L3 but that would add quite a bit of inductance for this path... Similarly to option B, can we then consider that the current will follow the path of lowest inductance and flow mostly through L2? If so, how to work with the PCB manufacturer for this design again since it is does not look like microstrip?

Questions:

  1. Feel free to comment and discuss any points/questions above. I may misunderstand some basic concepts.
  2. For option B and C, how does L4 come into play when calculating the trace impedance for L3 traces?
  3. For option B and C, if L4 cannot be considered as a solid reference plane, what to do to estimate the required trace width for controlled impedance, and how do we work with the PCB manufacturer?
  4. Does option B have any advantages over option C except that it allows to carry some power "tracks" which may not fit anywhere else in the PCB?

Thank you !

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  • \$\begingroup\$ TL;DR you are on the right track. Saturn PCB freeware can do most of this and more for you. Inductance varies with Length/width ratio typ 0.5 to 1 nH/mm and C varies with gap to track width ratio thus Zo = sqrt(L/C) to get thinner tracks on 50 Ohms you need thinner dielectric to maintain Zo. You can compute asymmetric buried track to planes. For best results differential tracks follow same path on adjacent layers with copper pours on either side and gnd thin guards between multiple pairs for GHz bus signals. But my effective reduces with higher frequency and low loss tangent FR4 is pref.’d \$\endgroup\$ Mar 9, 2021 at 21:20
  • \$\begingroup\$ Until you get experience with fab shop, it’s worth getting impedance testing so they adjust the D code trace widths to match FR4 batch if dielectric constant with TDR method on coupons outside area. You must provide drawing with specified impedance of critical traces. Then you get some feedback. \$\endgroup\$ Mar 9, 2021 at 21:22

2 Answers 2

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From Rick Hartley- You are correct about Option A, Layer 3 Impedance calculations will be made from trace width and its distance to the plane on L2, as well as to the plane on L4. The field coupling to L2 will be MUCH greater than the coupling to L4 (approx 80% to L2 & 20% to L4- energy couples by the square of the distance) This transmission line will function as an 'Offset Stripline' and should be calculated as such. Folks often describe impedance as the ratio of the Line Capacitance to Line Inductance. In reality it is the ratio of the E Field to the H Field. In this case the fields couple much tighter to L2 than to L4, but they do couple to both planes, hence 'Offset Stripline'.

That said, as transmission lines cross each other, in orthogonal directions, they will couple a small amount of energy into one another (Energy in the space from L3 to L2 will couple slightly into the space between L4 to L5). This coupling will cause a small amount of interference between lines. For that reason, at bit rates beyond 5 to 6 GBits I would consider stacking the board with each signal layer between a pair of Ground planes. That is not mandatory, but considering how many issues (Skin Effect, Loss tangent, etc.) high level GBit signals must content with, it's generally a good idea. My experience has been, with signal speeds up through a few GBits, this interference is not an issue.

As for Option B and C, in response to your last question, if this was a digital PC board I would go with Option B (power pours on signal layers). The reason was discussed later in the video with Robert Feranac, having alternating layers of Power/Ground/Power/Ground, etc through the board stack-up will usually improve power delivery, by increasing interplane capacitance and lowering overall inductance of the power bus. In my opinion, it's the lowering of inductance that does the most good (many reasons for that statement, not getting into that now- If you want to know more, attend on of my webinars, there is one coming in April, from Sierra Circuits). If this was an analog board, with routed power, I would use Ground pour on the signal layers, for obvious reasons. If it was a high layer count, GHz frequency RF board I would place only 1 signal layer between Ground planes.

Regarding impedance determination (Zo calculation) of Option B or C, I would handle each signal layer as 'Centered Stripline' or 'Single offset Stripline' (depending on the dielectric thicknesses from L2 to L3, L3 to L4 and L4 to L5). Remember, impedance is the ratio of coupled energy of the E & H fields of the lines. Even though the L3 fields do not see a complete plane on L4, there is enough copper on L4 to mostly contain the fields just as they are contained between L3 and L2, so from the standpoint of field structure both Option B and C look as though they are single stripline. As 'The Photon' pointed out, there is a very good, and continuous reference plane for L3 on L2 and one for L4 on L5. As a result, fields are mostly contained and all is well, below certain frequencies. Yes, there will be some interference between transmission lines in this overall cavity, but not enough to cause issues below a few GBits. The last project I worked on at L3 Avionics had a 4 GBit DDR memory structure, as well as other GBit level lines. We designed it in exactly this fashion and had no problems, including no EMI issues.

One key takeaway from this information should be to think in terms of 'Fields' NOT in terms of 'Current paths'. Energy in transmission lines, including the power bus, is in the Fields, which are in the 'SPACE' between the copper features.

Also, for those of you who are NOT fans of copper pours on signal layers, ask your assembly company (your CM) how they feel about continuous and balanced copper, both in and on all layers of a PC board. Balanced copper helps create even heating, prior to solder reflow, and helps prevent warp and twist. Food for thought!

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  • \$\begingroup\$ Thank you Rick for your answer and the few keys about the involved underlying concepts! Some extra research brought me to this article which helped me visualize the behavior (even if it is a different simulation). To make a connection between the Photon's answer and yours, how does the distance between L3 and L4 matter for option B and C? Even though I believe that a binary answer may be too simplistic: below 5 Gbits, would you still consider option B and C as relevant if L3 is about equidistant to L2 and L4? \$\endgroup\$
    – Marmoz
    Mar 28, 2021 at 9:53
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I recommend that if your traces are carrying signals fast enough to care about controlled impedance, you simply shouldn't use options B or C.

The problem is that whenever a track on L3 crosses a track on L4, it also crosses a break in the L4 power or ground plane. That means the return current for the L3 signal must find some other way around to get to the other side of the break.

It might not cause a radiation problem because any radiation from the gap is confined by the L5 plane ... or the radiation might find a way to the edge of the board and radiate.

But even if it doesn't radiate, it will cause a discontinuity for the transmission line on L3, and reflections for the signal on the L3 track. If controlled impedance is important for your design, then this is exactly what you're trying to avoid.

So just stick to option A and don't use B or C.

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  • \$\begingroup\$ Thank you. I'm a bit surprised because, if I understood correctly, Rick Hartley actually said in the video I pointed to in my first post that option B would be acceptable up to 2-3 GHz. Are there specific conditions to make it work as he suggested? I understand the general statement that a gap in a reference plane is a problem. However, in this case, it seems to me that it exists a very good continuous return path on L2. Why would current try to force its way into L4 then? \$\endgroup\$
    – Marmoz
    Mar 9, 2021 at 23:46
  • \$\begingroup\$ The return current will want to flow on both reference planes, roughly in proportion to the capacitance between the trace and each plane. If it can't do that then you have an impedance discontinuity. If the dielectric between L3 and L4 is much thicker than between L2 and L3 or between L4 and L5, then this might work okay up to ~1 GHz. If the dielectric layers are approximately equal thickness, I wouldn't do it above ~100 MHz. \$\endgroup\$
    – The Photon
    Mar 10, 2021 at 0:11

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