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I need some guidance on how to begin troubleshooting a specific problem with a bareboard. Board Info- Size-22"x26" Laminate-ITEQ Layers-30

In addition to standard bareboard ET (10v with 10Mohms isolation threshold), we also do HV test @ 500v (with isolation threshold of 500Mohms). It passes standard test, but fails HV test for pwr/gnd shorts. The only way it passes HV test is when we use voltage ramp up delay. Using Fluke 8845A to measure resistance, it will detect resistance between pwr and gnd (that should be isolated from each other), but quickly dissipates within 1 second. I then pick up probes and touchdown on the same pins and it no longer detects any resistance. I then switch polarity (switch probes) on the same pins and it picks up resistance again. What is causing this discharge?
Cu pour (not thieving) was added on all signal layers (.5oz. striplines with .008" dielectric to gnd) and on empty areas on power layers (1oz. with .004" dielectric to gnd). Cu pour have airgaps no less than .050" to nearest features. Blindly, we released another lot w/o the Cu pour to see if it resolves the issue. If we do find that removal of Cu pour fixes this issue, can someone detail what exactly is happening with the board; how is Cu pour creating the problem (which is TBD)?

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    \$\begingroup\$ See this recent question about in-board capacitance: electronics.stackexchange.com/questions/53554/… . In my answer there, I concluded its difficult to get high capacitance values. But that was for a 2-layer board. With 30 layers, you likely have plane-plane distances on the order of 0.05 mm. With this thickness and your 22x26" size, I calculate roughly 300 nF per power-ground pair. \$\endgroup\$ – The Photon Jan 16 '13 at 16:46
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Capacitance.

You will need to wait (to charge the capacitance) before making leakage measurements. As long as the "leakage" stops, this is just basic physics and in no way a defect on the board.

Removing the copper pour will reduce the capacitance, but in many applications that capacitance is a good thing, rather than a problem! Indeed, about a quarter of the components fitted to the board later, are only there to increase the capacitance between power and ground planes!

Discuss this "problem" with the customer : he will probably be glad to have it!

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  • \$\begingroup\$ Thank you "The Photon" and Brian D. for the response. So in a nutshell, I need to clarify with customer that HV failures are false. Will this capacitance pose future problems when board is energized and in use? Highly unlikely that the boards will ever see 500V in the field. \$\endgroup\$ – Walter Jan 16 '13 at 17:34
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    \$\begingroup\$ Or get his approval to ramp the voltage, or wait for the charge-up time. (Or add deliberate leakage to shorten the charge time, and remove it to measure. Depends on your test equipment). The capacitance can pose operational problems. If he isn't expecting it on high speed signals, it will slow them down and that is a design failure. But on power supplies, more capacitance is better. Only the customer can know for sure. He may have special design requirements that you don't know, and refuse to accept the copper pour - or he might be glad to have it. \$\endgroup\$ – Brian Drummond Jan 16 '13 at 17:52

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