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Self thaught electronics hobbyist, I might be missing/misunderstanding something obvious.

I'm designing a circuit and added a battery protection based on the Diodes Incorporated AP9101C (Product page).

I don't really understand how the FET's work in the "typical application circuit": enter image description here

As I understand this (and since both sides are meant to be "ground", this is a bit confusing), these are two N-type, enhancment FET's. So,

  • source should be at a lower potential than the drain,
  • Vgs should be above a certain voltage to conduct.

According to the pinout and the operation description, DO is used to control discharge and CO to control charging. enter image description here enter image description here Looking at the functional diagram, it seems no majory current is conducted through the chip itself, so whatever goes from/to P- from/to battery ground goes through the FET's. enter image description here

However, whichever direction the current flows, there's always one FET that is "reverse biased"(don't know the exact term). As far as I understood, FET's are not meant to be used bidirectional.

So, in case the battery is discharging, (conventional) current is flowing from P- to GNDbat. In that case, Q1 is in the correct direction, but Q2 is not. In that case, is the current through Q2 flowing through the body diode (the diode from source to drain?). Or am I misunderstanding something?

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    \$\begingroup\$ Enhancement-mode, not "enhanced". \$\endgroup\$
    – Hearth
    Commented Mar 10, 2021 at 13:05

1 Answer 1

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As far as I understood, FET's are not meant to be used bidirectional.

They sure can operate bidirectionally but, with one proviso; in the reverse direction, you cannot get the MOSFET to fully turn-off (because of the bulk diode) but, in all other respects, the MOSFET will turn-on to a low value \$R_{DS}\$ when the current is in either direction providing that the gate-source voltage (for N channels) is sufficiently positive: -

enter image description here

Picture above from here.

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  • \$\begingroup\$ So my understanding that "N enhancement FET's should have source connected to lowest potential" is not correct? This just makes sense from the point of requiring Vgs to be above a certain voltage to conduct? Is that correct? \$\endgroup\$
    – Dieter Vansteenwegen
    Commented Mar 10, 2021 at 13:10
  • \$\begingroup\$ @DieterVansteenwegenON4DD you can connect source to whatever potential you want but you'll always have diode conduction if the drain is about 0.7 volts lower than the source AND, you will have low ohmic conduction if the gate is sufficiently higher voltage compared to the source irrespective of the drain voltage (within reason). \$\endgroup\$
    – Andy aka
    Commented Mar 10, 2021 at 13:12
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    \$\begingroup\$ That makes sense and clears up some other things I wasn't sure about. Thanks! \$\endgroup\$
    – Dieter Vansteenwegen
    Commented Mar 10, 2021 at 13:19

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